HW-AFX-FF1760-500-G Xilinx Inc, HW-AFX-FF1760-500-G Datasheet - Page 18

• Manufacturer Part Number: HW-AFX-FF1760-500-G
• Description: BOARD DEV VIRTEX 5 FF1760
• Manufacturer: Xilinx Inc
• Type: FPGAr

Specifications of HW-AFX-FF1760-500-G

• Contents: *
• For Use With/related Products: Virtex™-5 LX FF1760
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Detailed Description
18
12. DUT Socket
13. Pin Breakout
The DUT socket (U1) contains the user FPGA. The DUT must be oriented using the P1
indicator on the board.
The pin breakout area is used to monitor or apply signals to each of the DUT pins. Headers
can be soldered to the breakout area to use with certain types of oscilloscope probes, for
either connecting function generators or wiring pins to the pin breakout area.
shows the clocks in the pin breakout area that connect to the DUT clock pads.
Table 7: Breakout Clock Pin Connections
Label
Caution!
pin damage, always use the vacuum tool provided when inserting or removing the Virtex-5
device. When using BGA packages, do not apply pressure to the device while activating the
socket. Doing so can damage the socket and/or the device.
Failure to insert the device to the proper orientation can damage the device. To avoid
IO_L4N_GC_VREF_3
IO_L4N_GC_VREF_4
IO_L2P_GC_VRN_3
IO_L2N_GC_VRP_3
IO_L7P_GC_VRN_4
IO_L7N_GC_VRP_4
IO _L7N _GC _3
IO _L6N _GC_3
IO_L3N_GC_3
IO_L5N_GC_3
IO_L8N_GC_3
IO_L5N_GC_4
IO_L3P_GC_3
IO_L4P_GC_3
IO_L5P_GC_3
IO_L6P_GC_3
IO_L7P_GC_3
IO_L8P_GC_3
IO_L4P_GC_4
IO_L5P_GC_4
Clock Name
www.xilinx.com
FF324
D10
C10
U14
U13
U10
V10
E10
C11
V11
E11
B11
D9
C8
A6
A7
C7
U9
E9
B8
B6
Pin Number for Package Type
Virtex-5 LX FPGA Prototype Platform
FF676
AD15
AD14
AB12
AC11
AD8
AC7
D15
E12
F12
E15
E10
E11
E16
E17
F10
E18
F19
F9
F8
E8
UG222 (v1.1) April 18, 2008
FF1153
AG17
AG16
AG15
AK19
AJ19
AF14
H15
G20
H13
H14
G21
G22
H12
G13
J16
J15
F20
J20
J21
J14
Table 7
FF1760
AM13
AM14
AN29
AN15
AN14
AP30
M28
M14
M16
K28
K29
N16
K13
L27
L15
L16
K30
L14
J30
J13
R