HW-V5-ML550-UNI-G Xilinx Inc, HW-V5-ML550-UNI-G Datasheet - Page 56

• Manufacturer Part Number: HW-V5-ML550-UNI-G
• Description: EVALUATION PLATFORM VIRTEX-5
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr
• Type: FPGAr

Specifications of HW-V5-ML550-UNI-G

• Contents: Development Platform, Power Supply, Loopback Board, CompactFlash Card, software and documentation
• Silicon Manufacturer: Xilinx
• Features: 64M X 8 DDR SDRAM Memory, Six Samtec LVDS Connectors
• Kit Contents: Board, Cable, PSU, CD, Docs
• Silicon Family Name: Virtex-5
• Silicon Core Number: XC5VLX50T-FFG1136
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: Virtex™-5 LXT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Appendix A: LVDS
LVDS Receive Connectors
Table A-4: LVDS Receive Connector #1 (P74)
56
Pin #
P74
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
1
2
3
4
5
6
7
8
9
LVDS_DATAIN_CLKCAP_08P
LVDS_DATAIN_CLKCAP_09P
LVDS_DATAIN_00N
LVDS_DATAIN_01N
LVDS_DATAIN_02N
LVDS_DATAIN_03N
LVDS_DATAIN_04N
LVDS_DATAIN_05N
LVDS_DATAIN_06N
LVDS_DATAIN_07N
LVDS_DATAIN_00P
LVDS_DATAIN_01P
LVDS_DATAIN_02P
LVDS_DATAIN_03P
LVDS_DATAIN_04P
LVDS_DATAIN_05P
LVDS_DATAIN_06P
LVDS_DATAIN_07P
RX Signal Name
GND
GND
GND
GND
GND
GND
GND
GND
Table A-4
connections for LVDS receive connector #2 (P6), and
LVDS receive connector #3 (P3). These connectors and their associated FPGA banks are
detailed on ML550 0381218 schematic pages 9, 10, and 11.
The clock divider U17 connections are shown in
schematic page 10. The multiply and divide circuitry (detailed on schematic sheet 12) is
discussed in
lists the connections for LVDS receive connector #1 (P74),
“LVDS Connectors,” page
Pin #
M31
H30
U25
U26
U27
U28
G31
R26
R27
K29
F31
E31
T25
T26
L29
P31
U9
J30
J31
www.xilinx.com
Bank #
U9
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
28.
Pin #
P74
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
Table A-5
LVDS_DATAIN_16N
LVDS_DATAIN_17N
LVDS_DATAIN_18N
LVDS_DATAIN_16P
LVDS_DATAIN_17P
LVDS_DATAIN_18P
RX Signal Name
Table A-6
ML550 Networking Interfaces Platform
GND
GND
GND
GND
GND
GND
GND
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
and associated with P6 on
lists the connections for
UG202 (v1.4) April 18, 2008
Table A-5
Pin #
H29
U30
G30
T30
F30
J29
U9
lists the
Bank #
U9
15
15
15
15
15
15
15
R