AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 45

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

Table 6-7. JTAG/ICE Connector J13 Signal Descriptions
AT91SAM9G45-EKES User Guide
Pin
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
VTref. 3.3V power
Vsupply. 3.3V power
nTRST TARGET RESET - Active-low output
signal that resets the target
GND
TDI TEST DATA INPUT - Serial data output line,
sampled on the rising edge of the TCK signal.
GND
TMS TEST MODE SELECT
GND
TCK TEST CLOCK - Output timing signal, for
synchronizing test logic and control register
access.
GND
RTCK - Input Return test clock signal from the
target.
GND
TDO JTAG TEST DATA OUTPUT - Serial data
input from the target.
GND
nSRST RESET
GND
RFU
GND
RFU
GND
Mnemonic
This is the target reference voltage. It is used to check if the target
has power, to create the logic-level reference for the input
comparators, and to control the output logic levels to the target. It is
normally fed from VDD on the target board and must not have a
series resistor.
This pin is not connected in SAM-ICE. It is reserved for compatibility
with other equipment. Connect to VDD or leave open in target
system.
JTAG Reset. Output from SAM-ICE to the Reset signal on the target
JTAG port. Typically connected to nTRST on the target CPU. This pin
is normally pulled HIGH on the target to avoid unintentional resets
when there is no connection.
Common ground
JTAG data input of target CPU. It is recommended that this pin is
pulled to a defined state on the target board. Typically connected to
TDI on target CPU.
Common ground
JTAG mode set input of target CPU. This pin should be pulled up on
the target. Typically connected to TMS on target CPU. Output signal
that sequences the target's JTAG state machine, sampled on the
rising edge of the TCK signal.
Common ground
JTAG clock signal to target CPU. It is recommended that this pin is
pulled to a defined state on the target board. Typically connected to
TCK on target CPU.
Common ground
Some targets must synchronize the JTAG inputs to internal clocks. To
assist in meeting this requirement, a returned and retimed TCK can
be used to dynamically control the TCK rate. SAM-ICE supports
adaptive clocking which waits for TCK changes to be echoed
correctly before making further changes. Connect to RTCK if
available, otherwise to GND
Common ground
JTAG data output from target CPU. Typically connected to TDO on
target CPU.
Common ground
Active-low reset signal. Target CPU reset signal
Common ground
This pin is not connected in SAM-ICE.
Common ground
This pin is not connected in SAM-ICE
Common ground
Description
6481B–ATARM–27-Nov-09
Connectors
6-5