HS38000EPI61H Renesas Electronics America, HS38000EPI61H Datasheet - Page 249

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HS38000EPI61H

Manufacturer Part Number
HS38000EPI61H
Description
DEV EMULATOR BASE UNIT H8/38000
Manufacturer
Renesas Electronics America
Type
Microcontrollerr
Datasheet

Specifications of HS38000EPI61H

Contents
E6000 Emulator and CD-ROM
For Use With/related Products
38000 Series
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
The following messages are displayed during test. This test consists of steps 1 to 20. This example assumes that
HS38000EPI61H + HS3800EBK61H is in use. Time required for this test depends on performance of the host
computer and PC interface in use (approximately 2 to 10 minutes).
228
Message
Loading driver .......................OK
Initializing driver ..................OK
Searching for interface card .........OK
Checking emulator is connected .........OK
FPGA Configuration .....................OK
01) Test Register:
02) Test DPRAM :
Main Board ID:
Emulation Board ID:
SUB board ID:
A) IDR0 Register .........................................OK
B) PAGE Register .........................................OK
C) TRACE G/A Register ....................................OK
D) PERFM G/A Register ....................................OK
E) CES G/A Register ......................................OK
F) IDR1 Register .........................................OK
G) IDR2 Register .........................................OK
H) BOC Control Register ..................................OK
I) Mode Setting Register .................................OK
J) HPC Control Register Test Circuit Register ............OK
K) Test Register 3 .......................................OK
A) Decode Test ...........................................OK
B) Marching Test .........................................OK
Copyright (C) 2004 Renesas Technology Corp.
H8/3800 E6000 Emulator Tests Vx.x.xx
H'5
H'15
H'f
Description
Test program start
message.
version number.
Shows that the PC
interface board is
correctly installed in
the host computer.
Shows that the E6000 is
correctly connected to
the host computer.
Shows the result of a
transfer of E6000
control logic data to
the FPGA (normal
completion).
Shows the check results
for the registers in the
E6000 (normal
completion).
Shows the results of
decoding test and
marching test for the
dual-port RAM in the
E6000 (normal
completion).
Shows the ID number of
the lower board of the
E6000.
Shows the ID number of
the upper board of the
E6000.
Shows the ID number of
the E6000 (expansion
I/O board).
Vx.x shows the

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