IPT-C2H-NIOS Altera, IPT-C2H-NIOS Datasheet - Page 35

• Manufacturer Part Number: IPT-C2H-NIOS
• Description: C2H COMPILER FOR NIOS II
• Manufacturer: Altera
• Series: Nios®IIr
• Type: Nios IIr

Specifications of IPT-C2H-NIOS

• Function: C to Hardware Compiler
• License: Initial License
• Software Application: IP CORE, NIOS Processor And Functions
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Figure 2–3. Performance Section of the C2H Build Report
Altera Corporation
November 2009
5.
The Performance section shows the performance characteristics of each
loop in the accelerated function. There are two metrics that determine a
loop's performance: loop latency and cycles per loop-iteration (CPLI).
Loop latency is the number of cycles required to fill the pipeline. CPLI is
the number of cycles required to complete one iteration of the loop,
assuming the pipeline is filled and no stalls occur. For example, consider
the case of an accelerated function with one loop with loop latency of 13
and CPLI value of 1. (These values can differ, depending on the memory
latency on your target board.) These numbers indicate that the pipeline
takes 13 cycles to fill; once the pipeline is filled, the pipeline generates a
new result every cycle.
1
Expand the Performance section and all subsections, as shown in
Figure
In general, the goal of optimizing an application for better
accelerator performance is to reduce loop latency and CPLI.
2–3.
9.1
Nios II C2H Compiler User Guide
Getting Started Tutorial
2–13