IPT-C2H-NIOS Altera, IPT-C2H-NIOS Datasheet - Page 61
IPT-C2H-NIOS
Manufacturer Part Number
IPT-C2H-NIOS
Description
C2H COMPILER FOR NIOS II
Manufacturer
Altera
Series
Nios®IIr
Type
Nios IIr
Datasheet
1.IPT-C2H-NIOS.pdf
(138 pages)
Specifications of IPT-C2H-NIOS
Function
C to Hardware Compiler
License
Initial License
Software Application
IP CORE, NIOS Processor And Functions
Core Architecture
FPGA
Core Sub-architecture
Cyclone
Rohs Compliant
NA
Lead Free Status / RoHS Status
Not applicable / Not applicable
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Figure 3–9. Address Generation for a Read Operation
Altera Corporation
November 2009
Each of these signals is registered at the master port interface of the
hardware accelerator. Logic within the accelerator synchronizes these
signals to produce coherent Avalon-MM master transfers at the master
port.
Address Computation
Consider the pointer dereference in the following code which performs a
read operation:
The C2H Compiler generates logic of the following form to compute the
address signal:
Figure 3–9
dereference for a read operation.
In
sizeof(int) is 4, i must be multiplied by four, which is equivalent to
left-shifting by 2 bits. Bitwise shift operators require no logic elements to
compute, and the result is not registered. (See section
Operations and Assignments” on page
ptr_to_int_i_address feeds registers that drive the address signals
on the Avalon-MM master port. As soon as the address signal
ptr_to_int_i_address is valid, read-enable control logic asserts the
signal ptr_to_int_i_read, which initiates a transfer on the master
Figure
int j = *(ptr_to_int + i);
ptr_to_int_i_addr = ptr_to_int + i * sizeof(int);
3–9, first, the address expression is evaluated. Assuming
shows an example of the logic created for this pointer
9.1
3–3.) The signal
C-to-Hardware Mapping Reference
Nios II C2H Compiler User Guide
“Unregistered
3–21
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