EVAL-AD1835EB Analog Devices Inc, EVAL-AD1835EB Datasheet - Page 11

• Manufacturer Part Number: EVAL-AD1835EB
• Description: BOARD EVAL FOR AD1835
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD1835EB

• Rohs Status: RoHS non-compliant

FUNCTIONAL OVERVIEW
ADCs
There are two ADC channels in the AD1835, configured as a
stereo pair. Each ADC has fully differential inputs. The ADC
section can operate at a sample rate of up to 96 kHz. The ADCs
include on-board digital decimation filters with 120 dB stop-band
attenuation and linear phase response, operating at an over-
sampling ratio of 128 (for 48 kHz operation) or 64 (for 96 kHz
operation).
ADC peak level information for each ADC may be read from
the ADC Peak 0 and ADC Peak 1 registers. The data is supplied
as a 6-bit word with a maximum range of 0 dB to –63 dB and a
resolution of 1 dB. The registers will hold peak information until
read; after reading, the registers are reset so that new peak
information can be acquired. Refer to the register description
for details of the format. The two ADC channels have a common
serial bit clock and a left-right framing clock. The clock signals
are all synchronous with the sample rate.
The ADC digital pins, ABCLK and ALRCLK, can be set to
operate as inputs or outputs by connecting the M/S pin to
ODVDD or DGND, respectively. When the pins are set as
outputs, the AD1835 will generate the timing signals. When
the pins are set as inputs, the timing must be generated by the
external audio controller.
DACs
The AD1835 has eight DAC channels arranged as four inde-
pendent stereo pairs, with eight fully differential analog outputs
for improved noise and distortion performance. Each channel
has its own independently programmable attenuator, adjustable
in 1024 linear steps. Digital inputs are supplied through four
serial data input pins (one for each stereo pair) and a common
frame (DLRCLK) and bit (DBLCK) clock. Alternatively, one
of the “packed data” modes may be used to access all eight
channels on a single TDM data pin. A stereo replicate feature is
included where the DAC data sent to the first DAC pair is also
sent to the other DACs in the part. The AD1835 can accept
DAC data at a sample rate of 192 kHz on DAC 1 only. The
stereo replicate feature can then be used to copy the audio data
to the other DACs.
REV. B
MCLK
12.288MHz
ADC OUTPUT
DAC INPUT
CLOCK SCALING
48kHz/96kHz/192kHz
48kHz/96kHz
2/3
1
2
Figure 2. Modulator Clocking Scheme
IMCLK = 24.576MHz
INTERPOLATION
OPTIONAL
FILTER
HPF
–11–
Each set of differential output pins sits at a dc level of V
swings ± 1.4 V for a 0 dB digital input signal. A single op amp
third order external low-pass filter is recommended to remove
high frequency noise present on the output pins, as well as to
provide differential-to-single-ended conversion. Note that the
use of op amps with low slew rate or low bandwidth may cause
high frequency noise and tones to fold down into the audio
band; care should be exercised in selecting these components.
The FILTD pin should be connected to an external grounded
capacitor. This pin is used to reduce the noise of the internal
DAC bias circuitry, thereby reducing the DAC output noise. In
some cases, this capacitor may be eliminated with little effect on
performance.
DAC and ADC Coding
The DAC and ADC output data stream is in a twos complement
encoded format. The word width can be selected from 16 bit,
20 bit, or 24 bit. The coding scheme is detailed in Table I.
Clock Signals
The DAC and ADC engines in the AD1835 are designed to
operate from a 24.576 MHz internal master clock (IMCLK).
This clock is used to generate 48 kHz and 96 kHz sampling on
the ADC and 48 kHz, 96 kHz, and 192 kHz on the DAC,
although the 192 kHz option is available only on one DAC pair.
The stereo replicate feature can be used to copy this DAC data
to the other DACs if required.
To facilitate the use of different MCLK values, the AD1835
provides a clock scaling feature. The MCLK scaler can be
programmed via the SPI port to scale the MCLK by a factor of
1 (pass through), 2 (doubling), or 2/3. The default setting of
the MCLK scaler is 2, which will generate 48 kHz sampling
from a 12.288 MHz MCLK. Additional sample rates can be
achieved by changing the MCLK value. For example, the CD
standard sampling frequency of 44.1 kHz can be achieved
using an 11.2896 kHz MCLK. Figure 2 shows the internal con-
figuration of the clock scaler and converter engines.
DAC ENGINE
ADC ENGINE
DECIMATOR/
MODULATOR
FILTER
-
Code
01111......1111
00000......0000
10000......0000
Table I. Coding Scheme
MODULATOR
DAC
Σ-∆
Level
+FS
0 (Ref Level)
–FS
ANALOG
OUTPUT
ANALOG
INPUT
AD1835
REF
and