EVAL-AD1835EB Analog Devices Inc, EVAL-AD1835EB Datasheet - Page 12

• Manufacturer Part Number: EVAL-AD1835EB
• Description: BOARD EVAL FOR AD1835
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD1835EB

• Rohs Status: RoHS non-compliant

AD1835
To maintain the highest performance possible, it is recommended
that the clock jitter of the master clock signal be limited to less
than 300 ps rms, measured using the edge-to-edge technique.
Even at these levels, extra noise or tones may appear in the
DAC outputs if the jitter spectrum contains large spectral peaks.
It is highly recommended that the master clock be generated by
an independent crystal oscillator. In addition, it is especially
important that the clock signal should not be passed through an
FPGA or other large digital chip before being applied to the
AD1835. In most cases, this will induce clock jitter due to the
fact that the clock signal is sharing common power and ground
connections with other unrelated digital output signals.
RESET and Power-Down
PD/RST will power down the chip and set the control registers to
their default settings. After PD/RST is de-asserted, an initialization
routine will run inside the AD1835 to clear all memories to zero.
This initialization lasts for approximately 20 LRCLK intervals.
During this time, it is recommended that no SPI writes occur.
Power Supply and Voltage Reference
The AD1835 is designed for 5 V supplies. Separate power supply
pins are provided for the analog and digital sections. These pins
should be bypassed with 100 nF ceramic chip capacitors, as
close to the pins as possible, to minimize noise pickup. A bulk
aluminum electrolytic capacitor of at least 22 µF should also be
provided on the same PC board as the codec. For critical
applications, improved performance will be obtained with
separate supplies for the analog and digital sections. If this is not
possible, it is recommended that the analog and digital supplies
be isolated by means of two ferrite beads in series with the bypass
capacitor of each supply. It is important that the analog supply
be as clean as possible.
The internal voltage reference is brought out on the FILTR pin
and should be bypassed as close as possible to the chip, with a
parallel combination of 10 µF and 100 nF. The reference voltage
may be used to bias external op amps to the common-mode
voltage of the analog input and output signal pins. The current
drawn from the FILTR pin should be limited to less than 50 µA.
Serial Control Port
The AD1835 has an SPI
programming the internal control registers for the ADCs and
DACs and for reading the ADC signal levels from the internal
peak detectors. The SPI control port is a 4-wire serial control
port. The format is similar to the Motorola SPI format except
the input data-word is 16 bits wide. The maximum serial bit
clock frequency is 12.5 MHz and may be completely asynchro-
nous to the sample rate of the ADCs and DACs. Figure 3 shows
the format of the SPI signal.
®
compatible control port to permit
–12–
Serial Data Ports—Data Format
The ADC serial data output mode defaults to the popular I
format, where the data is delayed by 1 BCLK interval from the
edge of the LRCLK. By changing Bits 6 to 8 in ADC Control
Register 2, the serial mode can be changed to right-justified (RJ),
left-justified DSP (DSP), or left-justified (LJ). In the RJ mode, it is
necessary to set Bits 4 and 5 to define the width of the data-word.
The DAC serial data input mode defaults to I
Bits 5, 6, and 7 in DAC Control Register 1, the mode can be
changed to RJ, DSP, LJ, Packed Mode 1, or Packed Mode 2.
The word width defaults to 24 bits but can be changed by
reprogramming Bits 3 and 4 in DAC Control Register 1.
Packed Modes
The AD1835 has a packed mode that allows a DSP or other con-
troller to write to all DACs and read all ADCs using one input
data pin and one output data pin. Packed Mode 256 refers to the
number of BCLKs in each frame. The LRCLK is low while
data from a left channel DAC or ADC is on the data pin and
high while data from a right channel DAC or ADC is on the
data pin. DAC data is applied on the DSDATA1 pin and ADC
data is available on the ASDATA pin. Figures 7 to 10 show the
timing for the packed mode. Packed mode is available only for
48 kHz and when the ADC is set as a master (M/S = 0).
Auxiliary (TDM) Mode
A special auxiliary mode is provided to allow three external stereo
ADCs to be interfaced to the AD1835 to provide 8-in/8-out
operation. In addition, this mode supports glueless interface
to a single SHARC DSP serial port, allowing a SHARC DSP to
access all eight channels of analog I/O. In this special mode,
many pins are redefined; see Table II for a list of redefined pins.
The auxiliary and the TDM interfaces are independently
configurable to operate as masters or slaves. When the auxiliary
interface is set as a master, by programming the aux mode bit in
ADC Control Register 2, the AUXLRCLK and AUXBCLK are
generated by the AD1835. When the auxiliary interface is set as
a slave, the AUXLRCLK and AUXBCLK need to be generated
by an external ADC as shown in Figure 13.
The TDM interface can be set to operate as a master or slave by
connecting the M/S pin to DGND or ODVDD, respectively. In
master mode, the FSTDM and BCLK signals are outputs and
are generated by the AD1835. In slave mode, the FSTDM
and BCLK are inputs and should be generated by the SHARC.
Slave mode operation is available for 48 kHz and 96 kHz operation
(based on a 12.288 MHz or 24.576 MHz MCLK), and master
mode operation is available for 48 kHz only.
2
S. By changing
REV. B
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