EVAL-AD5532EB Analog Devices Inc, EVAL-AD5532EB Datasheet - Page 16

• Manufacturer Part Number: EVAL-AD5532EB
• Description: BOARD EVAL FOR AD5532
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5532EB

• Rohs Status: RoHS non-compliant
• Number Of Dac's: 32
• Number Of Bits: 14
• Outputs And Type: 32, Single Ended
• Sampling Rate (per Second): 45k
• Data Interface: Serial
• Settling Time: 22µs
• Dac Type: Voltage
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD5532
• Lead Free Status / Rohs Status: Not Compliant

09/19/02 2:30 PM_GS
AD5532B
The power supply lines of the AD5532B should use as large a trace
as possible to provide low impedance paths and reduce the effects of
glitches on the power supply line. Fast switching signals such as
clocks should be shielded with digital ground to avoid radiating
noise to other parts of the board, and should never be run near
the reference inputs. A ground line routed between the D
SCLK lines will help reduce crosstalk between them (not required
on a multilayer board as there will be a separate ground plane,
but separating the lines will help).
Note that it is essential to minimize noise on V
lines. Particularly for optimum ISHA performance, the V
must be kept noise-free. Depending on the noise performance of
the board, a noise filtering capacitor may be required on the V
Revision History
Location
9/02—Data Sheet changed from REV. 0 to REV. A.
Term LFBGA updated to CSPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global
Changes to SERIAL INTERFACE table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Replaced Figure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Changes to Figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Updated BC-74 package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MAX
1.70
A1
TOP VIEW
12.00 BSC
74-Lead Chip Scale Ball Grid Array [CSPBGA]
SQ
IN
COMPLIANT TO JEDEC STANDARDS MO-192ABD-1
and REFIN
OUTLINE DIMENSIONS
Dimensions shown in millimeters
IN
IN
DETAIL A
line
and
IN
(BC-74)
BSC
1.00
0.30 MIN
–16–
line. If this capacitor is necessary, then for optimum throughput
it may be necessary to buffer the source that is driving V
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A microstrip
technique is by far the best, but not always possible with a double-
sided board. In this technique, the component side of the board
is dedicated to ground plane while signal traces are placed on the
solder side.
As is the case for all thin packages, care must be taken to avoid
flexing the package and to avoid a point load on the surface of
the package during the assembly process.
11 10 9 8 7 6 5 4 3 2 1
BALL DIAMETER
0.70
0.60
0.50
BOT TOM
VIEW
DETAIL A
1.00 BSC
SEATING
PLANE
A
B
C
D
E
F
G
H
J
K
L
INDEX AREA
A1 CORNER
10.00 BSC
0.20 MAX
COPLANARITY
SQ
IN
REV. A
.
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