EVAL-AD5532EB Analog Devices Inc, EVAL-AD5532EB Datasheet - Page 4

• Manufacturer Part Number: EVAL-AD5532EB
• Description: BOARD EVAL FOR AD5532
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5532EB

• Rohs Status: RoHS non-compliant
• Number Of Dac's: 32
• Number Of Bits: 14
• Outputs And Type: 32, Single Ended
• Sampling Rate (per Second): 45k
• Data Interface: Serial
• Settling Time: 22µs
• Dac Type: Voltage
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD5532
• Lead Free Status / Rohs Status: Not Compliant

AD5532B
Parameter
DAC AC CHARACTERISTICS
ISHA AC CHARACTERISTICS
NOTES
1
2
3
Specifications subject to change
TIMING CHARACTERISTICS
PARALLEL INTERFACE
Parameter
t
t
t
t
t
t
NOTES
1
2
Specifications subject to change without notice.
SERIAL INTERFACE
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
4
5
Specifications subject to change without notice.
AC CHARACTERISTICS
AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; OFF_IN = OV; All specifications T
See Terminology section.
B Version: Industrial temperature range –40°C to +85°C; typical at +25°C.
Guaranteed by design and characterization, not production tested.
1
2
3
4
5
6
See Parallel Interface Timing Diagram.
Guaranteed by design and characterization, not production tested.
CLKIN
1
2
3
4
5
6
7
8
9
10
11
12
See Serial Interface Timing Diagrams.
Guaranteed by design and characterization, not production tested.
In ISHA mode the maximum SCLK frequency is 20 MHz and the minimum pulsewidth is 20 ns.
These numbers are measured with the load circuit of Figure 2.
SYNC should be taken low while SCLK is low for readback.
4
4
Output Voltage Settling Time
OFFS_IN Settling Time
Digital-to-Analog Glitch Impulse
Digital Crosstalk
Analog Crosstalk
Digital Feedthrough
Output Noise Spectral Density @ 1 kHz
Output Voltage Settling Time
Acquisition Time
AC Crosstalk
5
3
1
1, 2
1, 2
3
Limit at T
(B Version)
0
0
50
50
20
7
Limit at T
(B Version)
14
28
28
15
50
15
5
5
20
60
400
400
7
without notice.
MIN
MIN
3
3
, T
, T
(V
DD
MAX
MAX
= +8 V to +16.5 V, V
Unit
ns min
ns min
ns min
ns min
ns min
ns min
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
AD5532B-1
B Version
22
10
1
5
1
0.2
400
3
16
5
SS
2
Conditions/Comments
CS to WR Setup Time
CS to WR Hold Time
CS Pulsewidth Low
WR Pulsewidth Low
A4–A0, CAL, OFFS_SEL to WR Setup Time
A4–A0, CAL, OFFS_SEL to WR Hold Time
Conditions/Comments
SCLK Frequency
SCLK High Pulsewidth
SCLK Low Pulsewidth
SYNC Falling Edge to SCLK Falling Edge Setup Time
SYNC Low Time
D
D
SYNC Falling Edge to SCLK Rising Edge Setup Time for Readback
SCLK Rising Edge to D
SCLK Falling Edge to D
10th SCLK Falling Edge to SYNC Falling Edge for Readback
24th SCLK Falling Edge to SYNC Falling Edge for DAC Mode Write
SCLK Falling Edge to SYNC Falling Edge for Readback
= –4.75 V to –16.5 V; AV
IN
IN
–4–
Setup Time
Hold Time
Unit
µs max
µs max
nV-s typ
nV-s typ
nV-s typ
nV-s typ
nV/√Hz typ
µs max
µs max
nV-s typ
MIN
to T
MAX
CC
, unless otherwise noted.)
OUT
OUT
= +4.75 V to +5.25 V; DV
Valid
High Impedance
Conditions/Comments
500 pF, 5 kΩ Load Full-Scale Change
500 pF, 5 kΩ Load; 0 V to 3 V Step
1 LSB Change Around Major Carry
Outputs Unloaded
CC
= +2.7 V to +5.25 V;
REV. A