AD9779-EBZ Analog Devices Inc, AD9779-EBZ Datasheet - Page 36

• Manufacturer Part Number: AD9779-EBZ
• Description: BOARD EVALUATION FOR AD9779
• Manufacturer: Analog Devices Inc

Specifications of AD9779-EBZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9776/AD9778/AD9779
If a clean sine clock is available, it can be transformer-coupled
to REFCLK, as shown in Figure 71. Use of a CMOS or TTL
clock is also acceptable for lower sample rates. It can be routed
through a CMOS to LVDS translator, then ac-coupled, as
described in this section. Alternatively, it can be transformer-
coupled and clamped, as shown in Figure 72.
A simple bias network for generating VCM is shown in
Figure 73. It is important to use CVDD18 and CGND for the
clock bias circuit. Any noise or other signal that is coupled onto
the clock is multiplied by the DAC digital input signal and can
degrade DAC performance.
INTERNAL PLL CLOCK MULTIPLIER/CLOCK
DISTRIBUTION
The internal clock structure on the devices allows the user to
drive the differential clock inputs with a clock at 1× or an
integer multiple of the input data rate or at the DAC output
sample rate. An internal PLL provides input clock multiplication
and provides all the internal clocks required for the interpolation
filters and data synchronization.
The internal clock architecture is shown in Figure 74. The
reference clock is the differential clock at Pin 5 and Pin 6. This
clock input can be run differentially or singled-ended by
driving Pin 5 with a clock signal and biasing Pin 6 to the
midswing point of the signal at Pin 5. The clock architecture
can be run in the following configurations:
TTL OR CMOS
CLK INPUT
287Ω
1kΩ
LVDS_N_IN
LVDS_P_IN
Figure 72. TTL or CMOS REFCLK Drive Circuit
Figure 73. REFCLK VCM Generator Circuit
Figure 71. LVDS REFCLK Drive Circuit
0.1μF
0.1μF
0.1μF
0.1μF
1nF
50Ω
50Ω
V
CM
V
50Ω
50Ω
1nF
= 400mV
CM
= 400mV
BAV99ZXCT
HIGH SPEED
DUAL DIODE
V
CM
CLK+
CLK–
= 400mV
CVDD18
CGND
CLK+
CLK–
Rev. A | Page 36 of 56
PLL Enabled (Register 0x09, Bit 7 = 1)
The PLL enable switch shown in Figure 74 is connected to the
junction of the N1 dividers (PLL VCO divide ratio) and N2
dividers (PLL loop divide ratio). Divider N3 determines the
interpolation rate of the DAC, and the ratio N3/N2 determines
the ratio of reference clock/input data rate. The VCO runs
optimally over the range of 1.0 GHz to 2.0 GHz, so that N1
keeps the speed of the VCO within this range, although the
DAC sample rate can be lower. The loop filter components are
entirely internal and no external compensation is necessary.
PLL Disabled (Register 0x09, Bit 7 = 0)
The PLL enable switch shown in Figure 74 is connected to the
reference clock input. The differential reference clock input is
the same as the DAC output sample rate. N3 determines the
interpolation rate.
REFERENCE CLOCK
(PINS 5 AND 6)
PLL ENABLE
DETECTION
PHASE
Figure 74. Internal Clock Architecture
0x09 (7)
DIVIDE RATIO
PLL LOOP
0x09 (4:3)
÷N2
INTERNAL DAC SAMPLE
LOOP FILTER
BANDWIDTH
INTERNAL
0x0A (4:0)
FILTER
LOOP
RATE CLOCK
DIVIDE RATIO
0x09 (6:5)
PLL VCO
÷N1
0x01 (7:6)
÷N3
VCO RANGE
0x08 (7:2)
VCO
ADC
DATACLK OUT (PIN 37)
INTERPOLATION
RATE
DAC
0x0A (7:5)
PLL CONTROL
VOLTAGE RANGE