AD9779-EBZ Analog Devices Inc, AD9779-EBZ Datasheet - Page 43

• Manufacturer Part Number: AD9779-EBZ
• Description: BOARD EVALUATION FOR AD9779
• Manufacturer: Analog Devices Inc

Specifications of AD9779-EBZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Specifications are given in Table 19 for the drift of input data set
up and hold time vs. temperature, as well as the data keep out
window (KOW). Note that although these specifications do
drift, the length of the keep out window, where input data is
invalid, changes very little over temperature.
Table 19. AD9779 Timing Specifications vs. Temperature
Timing
Parameter
REFCLK to DATA
DATACLK to DATA
SYNC_I to
REFCLK
SYNCHRONIZATION OF INPUT DATA TO DATACLK
OUTPUT (PIN 37)
Synchronizing the input data bus to the DATACLK out signal is
achieved by meeting the timing relationships between DATACLK
and DATA timing specified in Table 19. If the user is synchro-
nizing the input data to the DATACLK out, the sync input
(SYNC_I) signal does not need to be applied and can be ignored
(connect to GND).
SYNCHRONIZATION OF INPUT DATA TO THE
REFCLK INPUT (PIN 5 AND PIN 6) WITH PLL
ENABLED OR DISABLED
Synchronizing the input data bus to the REFCLK input requires
the use of the SYNC_I input pins (Pin 13 and Pin 14). If the
SYNC_I input is not used, there is a phase ambiguity between
the DATACLK out and the REFCLK in. This ambiguity matches
the interpolation rate in which the AD9779, for example, is
currently operating. Because input data is latched on the rising
edge of DATACLK, it is impossible for the user to determine
onto which one of the multiple internal DACCLK edges (as an
example, one of four edges in 4× interpolation) the input data
actually latches. For the user to specifically determine the exact
edge of REFCLK on which the data is being latched, a rising
edge must be periodically applied to SYNC_I. The frequency of
the SYNC_I signal must be equal to f
Temperature
−40°C
+25°C
+85°C
−40°C
+25°C
+85°C
−40°C to +85°C
REFCLK
SYNC_I
DAC
Min
t
(ns)
−0.8
−1.1
−1.3
+1.8
+2.1
+2.5
−0.2
S
/2
N
, N being an integer,
Figure 96. Valid Timing Relationship for SYNC_I to REFCLK
Min
t
(ns)
+2.2
+2.5
+2.9
−0.4
−0.7
−0.9
+1.0
H
Max
KOW
(ns)
+1.3
+1.4
+1.5
+1.3
+1.4
+1.5
+0.8
Rev. A | Page 43 of 56
t
DAC_SAMPLE
t
S
and must be no greater than DATACLK for proper
synchronization. There is no limit on how slow the SYNC_I
signal can be driven. As long as the set up and hold timing
relationship between SYNC_I and REFCLK given in Table 19 is
met, the input data is latched on the immediate next rising edge
of REFCLK. Note that a rising edge of DATACLK out occurs
concurrently with the next REFCLK rising edge, after a short
propagation delay. Although this propagation delay is not
specified, input data setup and hold timing information is given
with respect to REFCLK in and DATACLK out in Figure 92 to
Figure 95. Also, note that in 1× interpolation, because there is
no phase ambiguity, there is no need to use the SYNC_I signal.
Valid Timing Window
In addition to the timing requirements of SYNC_I with respect
to REFCLK, it is important to understand that the valid timing
window for SYNC_I is limited by the internal DAC sample rate.
This is shown in Figure 96. When the t
met, the valid timing window for SYNC_I extends only as far as
one period of the internal DAC sample rate (minus t
Failure to meet this timing specification can potentially result in
erroneous data being latched into the AD9779 digital inputs.
As an example, if the AD9779 input data rate is 122.88 MSPS
and the REFCLK is the same, with the AD9779 in 4× interpola-
tion, the DAC sample rate is 1/491.52 MHz or about 2 ns. With
a t
for SYNC_I of
The timing window of the digital input data to REFCLK can be
moved in increments of one internal REFCLK cycle by using
the REFCLK OFFSET register (Register 0x7, Bits<4:0>).
Because SYNC_I can be run at the same frequency as REFCLK
when the PLL is enabled, best practice suggests that in this con-
dition, REFCLK and SYNC_I originate from the same source.
This limits the variation in time between these two signals and
makes the overall timing budget easier to achieve. A slight delay
may be necessary on the REFCLK path in this configuration to
add more timing margin between REFCLK and SYNC_I (see
Table 19 for timing relationship).
t
S
t
DAC_SAMPLE
H
of −0.2 ns and t
2 ns − 0.8 ns = 1.2 ns
H
of 1.0 ns, this gives a valid timing window
AD9776/AD9778/AD9779
S
and t
H
requirements are
S
and t
H
).