ST92F150-EVAL STMicroelectronics, ST92F150-EVAL Datasheet - Page 296

• Manufacturer Part Number: ST92F150-EVAL
• Description: BOARD EVALUATION FOR ST9 SERIES
• Manufacturer: STMicroelectronics

Specifications of ST92F150-EVAL

• Processor To Be Evaluated: ST90158 and ST92F1x Daughter Board
• Interface Type: I2C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-2905

J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Figure 138. Local Loopback structure
10.9.3.8 Peripheral clock management
To work correctly, the encoder and decoder sec-
tions of the peripheral need an internal clock at
1MHz. This clock is used to evaluate the protocol
symbols timings in transmission and in reception.
The prescaled clock is obtained by dividing the
MCU internal clock frequency. The CLKSEL regis-
ter allows the selection of the right prescaling fac-
tor. The six least significant bits of the register
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9
VPWI toward the
J1850 decoder
JBLPD peripheral
VPWO from the
peripheral logic
OPTIONS.INPOL
manager
Polarity
Passive state
OPTIONS.LOOPB
(FREQ[5:0]) must be programmed with a value us-
ing the following formula:
MCU Internal Freq. = 1MHz * (FREQ[5:0] + 1).
Note: If the MCU internal clock frequency is lower
than 1MHz, the JBLPD is not able to work correct-
ly. If a frequency lower than 1MHz is used, the
user program must disable the JBLPD.
Note: When the MCU internal clock frequency or
the clock prescaler factor are changed, the JBLPD
could lose synchronization with the J1850 bus.
MCU
MCU VPWO
MCU VPWI
pin
pin