KS8721SL-EVAL Micrel Inc, KS8721SL-EVAL Datasheet - Page 21

• Manufacturer Part Number: KS8721SL-EVAL
• Description: BOARD EVAL EXPERIMENT KS8721SL
• Manufacturer: Micrel Inc

Specifications of KS8721SL-EVAL

• Main Purpose: Interface, Ethernet Controller (PHY and MAC)
• Embedded: No
• Utilized Ic / Part: KSZ8721SL
• Primary Attributes: 1 Port, 100BASE-TX/100BASE-FX/10BASE-T
• Secondary Attributes: MII, RMII, Auto MDI, MDIX, >130 Meter Cable Driver, LDO, IEEE802.3u Compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 576-1010

KS8721BL/SL (3.3V Single Power Supply 10/100BaseTX/FX MII Physical Layer Transceiver)
F
UNCTIONAL
100BaseTX Transmit
100BaseTX Receive
The 100BaseTX transmit function performs parallel to serial
conversion, NRZ to NRZI conversion, MLT-3 encoding and
transmission. The circuitry starts with a parallel to serial conversion,
which converts the 25 MHz, 4-bit nibbles into a 125 MHz serial bit
stream. The incoming data is clocked in at the positive edge of the
TXC signal. The serialized data is further converted from NRZ to
NRZI format, and then transmitted in MLT3 current output. The
output current is set by an external 1% 6.49 K
transformer ratio. It has a typical rise/fall times of 4 ns and complies
with the ANSI TP-PMD standard regarding amplitude balance,
overshoot and timing jitters. The wave-shaped 10BaseT output
driver is also incorporated into the 100BaseTX driver.
The 100BaseTX receive function performs adaptive equalization, DC
restoration, MLT-3 to NRZI conversion, data and clock recovery,
NRZI to NRZ conversion, and serial to parallel conversion. The
receiving side starts with the equalization filter to compensate inter-
symbol interference (ISI) over the twisted pair cable. Since the
amplitude loss and phase distortion are a function of the length of
the cable, the equalizer has to adjust its characteristic to optimize the
performance. In this design, the variable equalizer will make an
initial estimation based on comparisons of incoming signal strength
against some known cable characteristics, then tunes itself for
optimization. This is an ongoing process and can self adjust against
the environmental changes such as temperature variations.
The equalized signal then goes through a DC restoration and data
conversion block. The DC restoration circuit is used to compensate
effect of base line wander and improve the dynamic range. The
differential data conversion circuit converts the MLT3 format back to
NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125 MHz clock from the edges
of the NRZI signal. This recovered clock is then used to convert the
NRZI signal into the NRZ format. Finally, the NRZ serial data is
converted to 4-bit parallel 4B nibbles. A synchronized 25 MHz RXC is
generated so that the 4B nibbles is clocked out at the negative edge
of RCK25 and is valid for the receiver at the positive edge. When no
valid data is present, the clock recovery circuit is locked to the 25
M z reference clock and both TXC and RXC clocks continue to run.
D
ESCRIPTION
- 21 -
KS8721BL/SL Preliminary Rev 0.90
resistor for the 1: 1
Aug, 2003