KS8721SL-EVAL Micrel Inc, KS8721SL-EVAL Datasheet - Page 6

• Manufacturer Part Number: KS8721SL-EVAL
• Description: BOARD EVAL EXPERIMENT KS8721SL
• Manufacturer: Micrel Inc

Specifications of KS8721SL-EVAL

• Main Purpose: Interface, Ethernet Controller (PHY and MAC)
• Embedded: No
• Utilized Ic / Part: KSZ8721SL
• Primary Attributes: 1 Port, 100BASE-TX/100BASE-FX/10BASE-T
• Secondary Attributes: MII, RMII, Auto MDI, MDIX, >130 Meter Cable Driver, LDO, IEEE802.3u Compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 576-1010

KS8721BL/SL (3.3V Single Power Supply 10/100BaseTX/FX MII Physical Layer Transceiver)
P
Signal
Name
MDIO
MDC
RXD3 /
PHYAD1
RXD2 /
PHYAD2
RXD1 /
PHYAD3
RXD0 /
PHYAD4
VDDIO
GND
RXDV /
CRSDV /
PCS_LPBK
RXC
IN
D
ESCRIPTIONS
Pin
No.
1
2
3
4
5
6
7
8
9
10
I/O
I/O
I
Ipd/O MII Receive Data Output
Ipd/O MII Receive Data Output
Ipd/O MII Receive Data Output
Ipd/O MII Receive Data Output
Pwr
Gnd
Ipd/O MII Receive Data Valid Output
O
Description
Management Interface (MII) Data I/O
This pin requires an external 10K pull-up resistor.
Management Interface (MII) Clock Input
This pin is synchronous to the MDIO data interface
RXD [3..0], these bits are synchronous with
RXCLK. When RXDV is asserted, RXD [3..0]
presents valid data to MAC through the MII. RXD
[3..0] is invalid when RXDV is de-asserted.
The pull-up/pull-down value is latched as
PHYADDR [1] during reset. See “Strapping
Options” section for details.
The pull-up/pull-down value is latched as
PHYADDR [2] during reset. See “Strapping
Options” section for details.
The pull-up/pull-down value is latched as
PHYADDR [3] during reset. See “Strapping
Options” section for details.
The pull-up/pull-down value is latched as
PHYADDR [4] during reset. See “Strapping
Options” section for details.
Digital IO 2.5 /3.3V tolerance power supply
(See “Circuit design ref for power supply” section
for details)
Ground
The pull-up/pull-down value is latched as pcs_lpbk
during reset. See “Strapping Options” section for
details.
MII Receive Clock Output
Operating at:
25 MHz = 100 Mbps
2.5 MHz = 10 Mbps
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KS8721BL/SL Preliminary Rev 0.90
Aug, 2003