STEVAL-TCS003V1 STMicroelectronics, STEVAL-TCS003V1 Datasheet - Page 14

• Manufacturer Part Number: STEVAL-TCS003V1
• Description: BOARD DEMO EXPANDER STMPE2403
• Manufacturer: STMicroelectronics

Specifications of STEVAL-TCS003V1

• Main Purpose: Interface, GPIO Expander
• Embedded: No
• Utilized Ic / Part: STMPE2403
• Primary Attributes: 8/16/24-Bit 24-Port GPIO Expander over I2C
• Secondary Attributes: 3 8-Bit PWM Output for LEDs, Keyboard Matrix Scan, Special Key Support
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8206

I2C Interface
6
6.1
6.2
6.3
6.4
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I
The features that are supported by the I
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The address is selected by the state of two pins. The state of the pins will be read upon
reset and then the pins can be configured for normal operation. The pins will have a pull-up
or down to set the address. The I
access the registers in the STMPE2403.
Start condition
A Start condition is identified by a falling edge of SDATA while SCLK is stable at high state.
A Start condition must precede any data/command transfer. The device continuously
monitors for a Start condition and will not respond to any transaction unless one is
encountered.
Stop condition
A Stop condition is identified by a rising edge of SDATA while SCLK is stable at high state.
A Stop condition terminates communication between the slave device and bus master. A
read command that is followed by NoAck can be followed by a Stop condition to force the
slave device into idle mode. When the slave device is in idle mode, it is ready to receive the
next I
operation to registers.
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter
releases the SDATA after sending eight bits of data. During the ninth bit, the receiver pulls
the SDATA low to acknowledge the receipt of the eight bits of data. The receiver may leave
the SDATA in high state if it would to not acknowledge the receipt of the data.
Data input
The device samples the data input on SDATA on the rising edge of the SCLK. The SDATA
signal must be stable during the rising edge of SCLK and the SDATA signal must change
only when SCLK is driven low.
2
C Interface
I
Operates at 1.8V
Compliant to Philip I
Supports Standard (up to 100kbps) and Fast (up to 400kbps) modes.
7-bit and 10-bit device addressing modes
General Call
Start/Restart/Stop
Address up to 4 STMPE2403 devices via I
2
2
C Slave device
C transaction. A Stop condition at the end of a write command stops the write
2
C specification version 2.1
2
C interface module allows the connected host system to
2
C interface are as below:
2
C
STMPE2403