COP8SA-DM National Semiconductor, COP8SA-DM Datasheet
COP8SA-DM
Specifications of COP8SA-DM
Related parts for COP8SA-DM
COP8SA-DM Summary of contents
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... COP8™ MICROCONTROLLER COP8SAx Designer’s Guide Literature Number 620894-001 January 1997 ...
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REVISION RECORD RELEASE REVISION DATE -001 1/97 ii SUMMARY OF CHANGES First Release ...
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... For more detailed information, refer to the COP8 Feature Family User’s Manual. Chapter 3, DEVELOPMENT TOOLS, describes the range of development tools that are available for developing and testing application software that is run on the COP8SAx mi- crocontroller. Chapter 4, COP8SAx APPLICATION IDEAS, provides an overview of some design exam- ples using the COP8SAx microcontroller. Within these examples, the users can fi ...
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iv ...
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... Microcontroller CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.7.4 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 1.7.5 Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 1.7.6 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 1.7.7 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 Chapter 2 COP8SAx7 MICROCONTROLLER 2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.2 KEY FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.2.1 CPU Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2.2 Peripheral Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.3 I/O Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.4 Fully Static CMOS Design ...
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Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.8.9 Control ...
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JMP — Jump Absolute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82 2.18.20 JMPL — Jump ...
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... Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-137 2.23.4 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-138 2.23.5 Output Series Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-139 2.23.6 Oscillator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-139 2.23.7 Mechanical Shielding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-139 2.24 EMI REDUCTION ON THE COP8SAx7 . . . . . . . . . . . . . . . . . . . . . . . 2-140 2.24.1 Silicon Design Changes to Achieve Low EMI . . . . . . . . . . . 2-141 2.24.2 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-141 Chapter 3 DEVELOPMENT SUPPORT 3.1 SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2 iceMASTER (IM) IN-CIRCUIT EMULATION ...
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... CORDLESS PHONE APPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32 4.12.1 Typical Application Requirements . . . . . . . . . . . . . . . . . . . . . 4-33 4.13 COP8SAC7 BASED AUTOMATED SECURITY/MONITORING APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35 4.13.1 Typical Application Requirements . . . . . . . . . . . . . . . . . . . . . 4-36 4.14 COP8SAC7 Keyboard Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38 4.14.1 Typical Application Requirements . . . . . . . . . . . . . . . . . . . . . 4-39 4.14.2 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40 4.15 COP8SAA7 CLOSED LOOP TEMPERATURE CONTROL APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41 4.15.1 Primary System considerations: ...
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... Figure 1-8 External Oscillator 1-16 Figure 1-9 R/C Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 Figure 1-10 Phase Shift Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 Figure 2-1 COP8SAx7 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Figure 2-2 Connection Diagrams 2-6 Figure 2-3 Part Numbering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Figure 2-4 I/O Port Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Figure 2-5 I/O Port Configurations– ...
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... Figure 4-1 Test Circuit 4-2 Figure 4-2 Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Figure 4-3 MICROWIRE/PLUS Sample Protocol Timing . . . . . . . . . . . . . . . . . . . . 4-4 Figure 4-4 NM93C06-COP8SAx7 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Figure 4-5 Timer PWM Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 Figure 4-6 PWM Motor Control 4-12 Figure 4-7 Timer Capture Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 Figure 4-8 Power Wakeup Using An NPN Transistor ...
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CONTENTS ...
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WHAT IS A MICROCONTROLLER? Microcontroller is an highly integrated single-chip microcomputer. Some of the key elements of a microcontroller include a CPU to process information, program memory to store instructions, data memory to store information, system timing, and input/output ...
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Program Memory CPU Figure 1-1 Microcontroller General Block Diagram 1.2 WHAT DOES A MICROCONTROLLER REPLACE? A ...
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WHAT ARE MICROCONTROLLER APPLICATIONS? Microcontrollers applications ...
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Market Segment Consumer Children Basketball/Baseball Toys and Games Games Children Electronic Toys Darts Throws Juke Box Pinball Laser Gun Electronic Audio Greeting Cards Audio Items Electronic Musical Equipment Electronic Small Appliances: Appliances Irons and Tools Coffee Makers Digital Scales Microwave ...
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Market Segment Applications Personal Communications Cordless Phone (base/handset) Phone Dialer Answering Machine Feature Phone PBX Card CB Radios/Digital Tuners Cable Converter Medical Monitors Thermometer Pressure Monitors Various Portable Monitors Medical Bed-side Pump/Timers Equipment Ultrasonic Imaging System Analyzers (chemical, data) Electronic ...
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Market Segment Applications Automotive Radio/Tape Deck Controls Window, Seat, Mirror, and Door Controls Climate Controls Headlight/Antenna Power Steering Anti Theft Slave Controllers 1.4 WHAT IS THE DIFFERENCE BETWEEN A MICROCONTROLLER AND A MICROPROCESSOR? The broad category of microcomputers is divide ...
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This means that an instruction fetch cannot overlap a data access from memory. The obvious advantage of a Von Neumann ...
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Program Memory Address Register CPU Data Register Figure 1-2 Microcontroller Operation 1-8 MICROCONTROLLER BASICS Data Bus Data Memory Address Bus I/O ...
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Program Memory Program memory contains the microcontroller program. There are several types of program memory—ROM, OTP/EPROM, EEPROM. Stack Figure 1-3 Program Memory Section Structure The number of bits per address location and number of memory locations varies from one ...
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Each byte in program memory contains an instruction like ADD or JMP, represented by a code or opcode (example: 033 = ADD). Instructions are stored in the order to be executed. For example: LD A,#00 INC A JMP 00 These ...
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Data Memory Memory Address Register Figure 1-4 Separate Data and Code Space data memory. The data pointer (PTR) is loaded with the address of a byte of data in memory. To access the byte of data, the pointer can be ...
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POP instructions. Stack Pointer 1.7.3 Microcontroller CPU The key function of a CPU is to perform instruction fetch/decode/execute. Fetch The program counter (PC) addresses a location in program memory con- taining an instruction. This instruction is latched into a special ...
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Timer run, which tells microcontroller to start the timer. Accumulator vs Register An accumulator-based microcontroller operates in a manner different from a register- based microcontroller. The difference is due to the different ALU architectures. The most common are: 1. ...
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Addent #1 Addent #2 Figure 1-6 Adding Two Numbers Using Register Based Machine However, the accumulator-based machine requires operands to be moved into the accumulator before instructions are executed. Which takes longer in the end? It depends on how much ...
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... The instruction cycle time differs for various microcontrollers. It also differs for various instructions. Microcontroller manufacturers specify a minimum instruction cycle time. For example, for the COP8SAC7, the instruction cycle time This means that the fastest instructions are executed with the microcontroller operating at the maximum frequency ...
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External Clock Circuitry Clock Generator 1.7.5 Oscillator Circuits Typically there are three types of clock oscillator options available: external oscillator, R/C oscillator, or crystal oscillator. External Oscillator An external square wave clock source is generated outside and presented to the ...
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... The Pierce oscillator has one disadvantage. The amplifier used in the circuit must have high gain to compensate for gain losses in the circuitry surrounding the crystal. Figure 1-10 shows the classic phase shift oscillator found not only on the COP8SAx7 but on most other microcontroller circuits the simplest oscillator in terms of component complexity. ...
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Latches Ports Memory Mapped I/O or Ports User-Configurable I/O Dedicated I/O 1-18 MICROCONTROLLER BASICS output voltage on the pin corresponds to a single bit of information. Often used to store outgoing/incoming bits. A port is a group of pins used ...
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Each microcontroller has a set of instructions. The user can organize particular instructions in a logical order to create a program. The microcontroller follows this program to perform a given task. The contents of a microcontroller instruction set vary with ...
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Register Indirect Post-Increment or Post-Decrement Indexed Addressing 1.7.7 Programming Routines/Subroutines A routine is a segment of code which performs a specific function. A subroutine is a segment of code which performs a specific part of function. A subroutine is usually ...
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Interrupt Routines There are two methods to get the interrupt routines: 1. Without a Vector Table Polling—All interrupts cause an immediate jump to a single location in mem- ...
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Saving and restoring of the microcontroller state during interrupts or when switching between different tasks. Example of an interrupt routine: INTERRUPT; PUSH A PUSH CNTRL PUSH PSW IFBIT 0, IPND JP TIMERINT IFBIT 1, IPND JP EXTERNALINT IFBIT 2, IPND ...
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Assembler The assembler is a software program that converts a source program into an object file. In other words, it converts ASCII representation of instructions to binary representation. 2. Assembler Inputs/Outputs Source File - ASCII file containing a software ...
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Linker The linker is a software program that combines separate object files produced by the assembler into a single object file. The linker allows the user to create separate code modules for different sections of code. It also allows ...
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A simulator is software program/model which acts like a hardware device. Code written for the device is executed in the software model exactly as it would be executed in the device. Key features of a simulator include: 1. Can execute ...
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Following is the typical path for developing microcontroller programs: 1-26 MICROCONTROLLER BASICS EDITOR ENTER PROGRAM COMPILE PROGRAM ASSEMBLE PROGRAM LINK PROGRAM SIMULATE PROGRAM EMULATE PROGRAM WITH TARGET SYSTEM ...
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... Crystal/resonator oscillator — Crystal/resonator oscillator with on-chip bias resistor — External oscillator — Internal R/C oscillator • Internal power-on reset - user selectable • WATCHDOG and clock monitor logic - user selectable • high current outputs COP8SAx7 MICROCONTROLLER COP8SAx7 MICROCONTROLLER Chapter 2 2-1 ...
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... Default VIS (default interrupt) • 8-bit stack pointer SP (stack in RAM) • Two 8-bit register indirect data memory pointers • True bit manipulation • Memory-mapped I/O • BCD arithmetic instructions 2-2 COP8SAx7 MICROCONTROLLER Package and I/O Package Types Number of I/O 128 20 DIP/SO 28 DIP/SO ...
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... Two power saving modes: HALT and IDLE 2.2.5 Temperature Ranges 0˚C to +70˚C, –40˚C to +85˚C, and –40˚C to +125˚C 2.2.6 Development Support • Windowed packages for DIP and PLCC • Real-time emulation and full program debug offered by MetaLink Development System COP8SAx7 MICROCONTROLLER 2-3 ...
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... ICNTRL COND DETECT CNTRL CPU REGISTERS Figure 2-1 COP8SAx7 Block Diagram 2.4 ARCHITECTURE The COPSAx7 family is based on a modified Harvard architecture, which allows data tables to be accessed directly from program memory. This is very important with modern microcontroller-based applications, since program memory is usually ROM or EPROM, while data memory is usually RAM ...
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... G0/INT CKI 5 RESET GND G3/T1A C3 2 G4/SO 3 G2/T1B 4 G5/SK G1/WD G6/SI 5 G0/INT G7/CKO 6 CKI 7 RESET Vcc 8 GND COP8SAx7 MICROCONTROLLER 20 G3/T1A 19 G2/T1B 18 G1/WD 17 G0/INT 20-PIN RESET 16 DIP/SO GND Top View G3/T1A G2/T1B 37 36 G1/WD 35 G0/INT 34 RESET 40-PIN 33 GND DIP Top View 2-5 ...
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... CKI 44-PIN F2 11 PLCC Top View Family Indicator Feature Set Indicator Program Memory Size No. of Pins Figure 2-3 Part Numbering Scheme 2-6 COP8SAx7 MICROCONTROLLER G0/INT CKI RESET CC 37 GND Figure 2-2 Connection Diagrams COP8SAA716M9 Package Type J = Windowed Ceramic PLCC M = SOIC N = DIP ...
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... COP8SAB720N8 20N COP8SAC720N8 28N COP8SAB728N8 28N COP8SAC728N8 COP8SAC740N8 COP8SAC744V8 COP8SAC7VEJ8 COP8SAC720M7 COP8SAC728M7 COP8SAC720N7 COP8SAC728N7 COP8SAC740N7 COP8SAC744V7 COP8SAC7VEJ7 COP8SAx7 MICROCONTROLLER 4k EPROM 4k EPROM Windowed Device Order Number 20M 28M 20N COP8SAC720Q9 20Q 28N COP8SAC728Q9 28Q 40N COP8SAC740Q9 40Q 44V COP8SAC744J9 44PQFP 20M ...
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... Port L pins. The unavailable pins are not terminated. A read operation these unterminated pins will return unpredictable values. To minimize current drain, the unavailable pins must be programmed as outputs. 2-8 COP8SAx7 MICROCONTROLLER and GND pins must be connected. CC DATA Port Set-Up ...
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... PORT L, G, AND C, F PORT L, G, AND C, F PORT L, G, AND C, F DATA DATA DATA REGISTER REGISTER REGISTER CONFIGURATION REGISTER Port read into a RAM address location Config Reg. Data Reg. CLKDLY HALT Alternate SK IDLE COP8SAx7 MICROCONTROLLER Weak Pullup (Software Selectable) 2-9 ...
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... Port 8-bit I/O port. The 40-pin device does not have a full complement of Port C pins. The unavailable pins are not terminated. A read operation on these unterminated pins will return unpredictable values. Only the COP8SAC7 device contains Port C. The 20/28 pin devices do not offer Port C. On these devices, the associated Port C Data and Confi ...
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... RAM address 06F Hex (devices with 128 bytes of RAM PORT L, G, AND C, F PORT L, G, AND C, F PORT L, G, AND C, F DATA DATA DATA REGISTER REGISTER REGISTER 0 = Pullup disable 1 = Pullup enabled CONFIGURATION REGISTER 0 = Input Port read into a RAM address location COP8SAx7 MICROCONTROLLER Weak Pullup (Software Selectable) 2-11 ...
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... A and PC) are memory mapped; therefore, I/O bits and register bits can be directly and individually set, reset and tested. The accumulator (A) bits can also be directly and individually tested. RAM contents are undefined upon power-up. 2-12 COP8SAx7 MICROCONTROLLER Program Data Memory Memory (Bytes) ...
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... The 8 bytes of user storage space are outside the normal address range of the device, and cannot be accessed by software. This allows for the storage of non-secure information. Typical uses of this are serial numbers, date codes, copyright informations, software version, or lot numbers. Bit 4 Bit 3 Bit 2 COP8SAx7 MICROCONTROLLER Bit 1 Bit 0 2-13 ...
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... EPROM program memory and ECON register is inhibited. The ECON register is readable regardless of the state of the security bit. If security is being used recommended that all other bits in the ECON register be programmed first. Then the security bit can be programmed. 2-14 COP8SAx7 MICROCONTROLLER ...
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... RANDOM after RESET at power-on WKEN, WKEDG: CLEARED WKPND: RANDOM SP (Stack Pointer): Initialized to RAM address 02F Hex (devices with 64 bytes of RAM), or ini- tialized to RAM address 06F Hex (devices with 128 bytes of RAM). INTERNAL RESET ECON Bit 6 Figure 2-7 Reset Logic COP8SAx7 MICROCONTROLLER 2-15 ...
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... RESET may also be used to cause an exit from the HALT mode. With a slowly rising power supply, the device may start running before VCC is within the guaranteed range. In this case, the user must provide an external RC network and a diode shown in Figure 2-8. Figure 2-8 Reset Circuit Using External Reset 2-16 COP8SAx7 MICROCONTROLLER ...
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... V The contents of data registers and RAM are unknown following the on-chip reset External RESET Timer t rises to a voltage level above 2.0V. The on-chip the minimum level for the CC remains above 2.0V. CC COP8SAx7 MICROCONTROLLER (V rise time The CC 2-17 ...
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... On-Chip Reset V /RESET max t min Figure 2-10 Reset Timing (Power-On Reset enabled) With V Figure 2-11 Reset Circuit Using Power-On Reset 2-18 COP8SAx7 MICROCONTROLLER NOT ACTIVE ACTIVE x is the minimum operating voltage for the frequency of operation = 50 ms 4096 COP8 RESET Tied to RESET ...
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... Table 2-2 Oscillator Option Oscillator Option 0 External Oscillator 0 Crystal Oscillator without bias resistor 1 R/C Oscillator 1 Crystal Oscillator with bias resistor ) C1 (pF) C2 (pF 30–36 1 100 100-156 R1 C1 WITHOUT ON-CHIP BIAS RESISTOR Figure 2-12 Crystal Oscillator COP8SAx7 MICROCONTROLLER = 25˚ CKI Freq (MHz 0.455 2-19 ...
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... CKI pin. Figure 2-14 shows the R/C oscillator configuration. Table 2-4 R/C Oscillator Configuration, -40˚C to +85˚C, V External Capacitor (pF 150 TBD 2-20 COP8SAx7 MICROCONTROLLER INPUT/or HALT EXTERNAL Restart CLOCK Figure 2-13 External Oscillator OSC Freq Variation of 35% R/C OSC Freq (MHz) 5 ...
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... Timer T1 mode control bit T1C3 Timer T1 mode control bit T1C3 T1C2 Bit 7 (On-chip INPUT/or HALT Restart For operation at maximum R/C oscillator frequence Figure 2-14 R/C Oscillator T1C1 T1C0 MSEL IEDG COP8SAx7 MICROCONTROLLER Open INPUT/or R/C) HALT Restart SL1 SL0 Bit 0 2-21 ...
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... T0EN Timer T0 Interrupt Enable (Bit 12 toggle) T0PND Timer T0 Interrupt pending LPEN L Port Interrupt Enable (Multi-Input Wakeup/Interrupt) Bit 7 could be used as a general purpose status flag Unused LPEN T0PND T0EN Bit 7 2-22 COP8SAx7 MICROCONTROLLER BUSY EXEN Bit 0 WPND WEN T1PNDB T1ENB GIE Bit 0 ...
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... PWM parameters require updating. This capability is provided by the fact that the timer has two separate 16 -bit reload registers. One of the reload registers contains the "ON" timer while the other holds the "OFF" time. By contrast, a microcontroller that has . The user cannot C translates to less software COP8SAx7 MICROCONTROLLER 2-23 ...
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... R1A register to be reloaded into the timer. Setting the timer enable flag T1ENB will cause an interrupt when a timer underflow causes the R1B register to be reloaded into the timer. Resetting the timer enable flags will disable the associated interrupts. 2-24 COP8SAx7 MICROCONTROLLER 16 BIT AUTO RELOAD REGISTER TIME 1 TIMER ...
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... By saving the timer value when the external event occurs, the time of the TIMER 16 BIT AUTO UNDERFLOW RELOAD REGISTER INTERRUPTS ON TIME 16 BIT TIMER/ COUNTER EDGE SELECTOR LOGIC 16 BIT AUTO RELOAD REGISTER OFF TIME COP8SAx7 MICROCONTROLLER EXT CLK T1A T1B 2-25 ...
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... Input Capture mode, the user must check both the T1PNDA and T1C0 pending flags in order to determine whether a T1A input capture or a timer underflow (or both) caused the interrupt. Figure 2-17 shows a block diagram of the timer in Input Capture mode. Figure 2-17 Timer in Input Capture Mode 2-26 COP8SAx7 MICROCONTROLLER T1A INPUTCAPTURE INTERRUPT REGISTER R1A ...
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... Pos. T1A Edge or Timer Underflow Pos. T1A Edge or Timer Under- flow Neg. T1A Edge or Timer Underflow Neg. T1A Edge or Timer Underflow COP8SAx7 MICROCONTROLLER Interrupt B Timer Source Counts On Pos. T1B T1A Pos. Edge Edge Pos. T1B T1A Neg. Edge Edge ...
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... The IDLE timer is used to generate a fixed delay to ensure that the oscillator has indeed 2-28 COP8SAx7 MICROCONTROLLER (V = 2.0V) without altering the state of the r ...
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... The device is placed in the IDLE mode by writing a “1” to the IDLE flag (G6 data bit). In this mode, all activities, except the associated on-board oscillator circuitry and the IDLE Timer T0, are stopped. DEVICE IN HALT MODE Unaltered: RAM Reg’s Function Registers Timers Ports PORT L RESET RAM COP8SAx7 MICROCONTROLLER 256 t C DEVICE ACTIVE CKO (G7) 2-29 ...
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... HALT or IDLE modes. IDLE TIMER CONTENTS OSC: DEVICE ACTIVE . . . SBIT 6, PORTGD NOP NOP Figure 2-19 Wakeup From IDLE 2-30 COP8SAx7 MICROCONTROLLER = the IDLE Timer toggles. C DELAY DEVICE IN IDLE MODE Unaltered: RAM Reg’s Function Active: Registers Timers T0 ...
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... Without multi-input wakeup, the microcontroller would be required to keep its software and code running constantly (Figure 2-21). INTERNAL DATA BUS ............................ 7 0 WKEN 0 7 LPEN BIT IN ICNTRL REG T0 INTERRUPT LOGIC COP8SAx7 MICROCONTROLLER IDLE HALT CKI CK0 OSC CKT ...
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... HALT mode (Figure 2-21). With features such as Multi-Input Wake-up, HALT and IDLE, and low voltage and current drain capabilities, National’s COP8SAx7 family of 8-bit microcontrollers is doing its part to reduce power consumption. And with “current” trends pointing to an environment where less is indeed more, that’s putting real power back in the hands of today’ ...
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... WKEN and WKEDG are all read/write registers, and are cleared at reset. WKPND register contains random value after reset. 2.13 INTERRUPTS 2.13.1 Introduction The device supports eight vectored interrupts. Interrupt sources include Timer 1, Timer T0, Port L Wakeup, Software Trap, MICROWIRE/PLUS, and External Input. COP8SAx7 MICROCONTROLLER 2-33 ...
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... The state of the interrupt enable bit, combined with the GIE bit determines whether an active pending flag actually triggers an interrupt. All of the maskable interrupt pending and enable bits are contained in mapped control registers, and thus can be controlled by the software. 2-34 COP8SAx7 MICROCONTROLLER PENDING FLAG INTERRUPT ENABLE INTERRUPT GIE ...
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... The interrupt service routine stored at location 00FF Hex should use the VIS instruction to determine the cause of the interrupt, and jump to the interrupt handling routine corresponding to the highest priority enabled and active interrupt. Alternately, the user may choose to poll all interrupt pending and enable bits to determine the source(s) of the COP8SAx7 MICROCONTROLLER 2-35 ...
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... Table 2-5 shows the types of interrupts, the interrupt arbitration ranking, and the locations of the corresponding vectors in the vector table. The vector table should be filled by the user with the memory locations of the specific interrupt service routines. For example, if the Software Trap routine is located at 0310 2-36 COP8SAx7 MICROCONTROLLER ...
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... Future 0yF0 - 0yF1 Future 0yEE - 0yEF Future 0yEC - 0yED Future 0yEA - 0yEB Future 0yE8 - 0yE9 Future 0yE6 - 0yE7 Future 0yE4 - 0yE5 Port L Edge 0yE2 - 0yE3 VIS Instruction 0yE0 - 0yE1 Execution without any inter- rupts COP8SAx7 MICROCONTROLLER VECTOR* ADDRESS (Hi-Low Byte) 2-37 ...
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... Figure 2-23 illustrates the different steps performed by the VIS instruction. Figure 2-24 shows a flowchart for the VIS instruction. INTERRUPT after an interrupt ABRITRATION LOGIC (generates an even number between E0 and FE STARTING ADDRESS HIGH 2-38 COP8SAx7 MICROCONTROLLER 0FF VIS Interrupt Vector VIS HIGH STARTING BIT 7:0 ADDRESS LOW INTERRUPT SERVICE ...
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... ACTIVE? JUMP TO VECTOR AT 0yE0/0yE1 END The non-maskable interrupt pending flag is cleared by the RPND (Reset Non-Maskable Pending Bit) instruction (under certain conditions) and upon RESET. JUMP TO VECTOR AT 0yFE/0yFF JUMP TO VECTOR AT 0yFA/0yFB JUMP TO VECTOR AT 0yE2/0yE3 Figure 2-24 VIS Flow Chart COP8SAx7 MICROCONTROLLER 2-39 ...
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... SERVICE . . . SERVICE: RBIT, EXPND, PSW . . . RET I 2-40 COP8SAx7 MICROCONTROLLER =00EF =00EE 0,PORTGC 0,PORTGD ; G0 pin configured Hi-Z IEDG, CNTRL ; Ext interrupt polarity: falling edge GIE, PSW ; Set the GIE bit EXEN, PSW ; Enable the external interrupt WAIT ; Wait for external interrupt ...
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... RETI or RET. This is because the return address stored on the stack is the address of the INTR instruction that triggered the interrupt. The program must skip that instruction in order to proceed with the next one. Otherwise, an infinite loop of Software Traps and returns will occur. COP8SAx7 MICROCONTROLLER 2-41 ...
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... Software Trap. The Software Trap should end with two RPND instructions followed by a re- start procedure. 2. Maskable interrupts, triggered by an on-chip peripheral block or an external device connected to the device. Under ordinary conditions, a maskable inter- 2-42 COP8SAx7 MICROCONTROLLER ...
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... Bits and 1 of the WDSVR register represent the 5-bit Key Data field. The key data is fixed at 01100. Bit 0 of the WDSVR Register is the Clock Monitor Select bit. Clock Key Data Monitor COP8SAx7 MICROCONTROLLER 2-43 ...
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... WDSVR Register is also counted as a WATCHDOG service. The WATCHDOG has an output pin associated with it. This is the WDOUT pin, on pin 1 of the port G. WDOUT is active low. The WDOUT pin has a weak pullup in the inactive 2-44 COP8SAx7 MICROCONTROLLER WDSVR Service Window Bit 6 ...
Page 83
... Subsequent WATCHDOG services must match all three data fields in WDSVR in order to avoid WATCHDOG errors. Clock Monitor Match Valid Service: Restart Service Window Don't Care Error: Generate WATCHDOG Output Don't Care Error: Generate WATCHDOG Output Mismatch Error: Generate WATCHDOG Output COP8SAx7 MICROCONTROLLER Action –32 t clock cycles 2-45 ...
Page 84
... POP. The stack pointer is initialized to RAM location 06F Hex during reset. Consequently, if there are more returns than calls, the stack pointer will point to addresses 070 and 071 Hex (which are undefined RAM). Undefined RAM 2-46 COP8SAx7 MICROCONTROLLER ...
Page 85
... Operating the MICROWIRE/PLUS arrangement with the internal clock source is called the Master mode of operation. Similarly, operating the MICROWIRE/PLUS arrangement with an external shift clock is called the Slave mode of operation. CHIP SELECT LINES LCD DISPLAY EEPROM DRIVER COP8SAx7 MICROCONTROLLER I/O VF/LED LINES DISPLAY DRIVER COP8 (SLAVE 2-47 ...
Page 86
... The SO and SK pins must also be selected as outputs by setting appropriate bits in the Port G configuration register. In the slave mode, the shift clock stops after 8 clock pulses. Table 2-10 summarizes the bit settings required for Master mode of operation. 2-48 COP8SAx7 MICROCONTROLLER SL0 SK period 0 ...
Page 87
... SK signal. Setting the SKSEL flag selects the alternate SK clock. The SKSEL is mapped into the G6 configuration bit. The SKSEL flag will power up in the reset condition, selecting the normal SK signal Fun. Fun Int TRI-STATE Int Ext TRI-STATE Ext. SK COP8SAx7 MICROCONTROLLER Operation MICROWIRE/PLUS Master MICROWIRE/PLUS Master MICROWIRE/PLUS Slave MICROWIRE/PLUS Slave 2-49 ...
Page 88
... Figure 2-26 MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK Mode, SK Idle SK Bit 7 SO (MSB) Bit 7 SI (MSB) Figure 2-27 MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK 2-50 COP8SAx7 MICROCONTROLLER SO Clocked G5 out on: Data Bit 0 SK Falling edge 0 SK Rising edge 1 SK Rising edge ...
Page 89
... Bit 4 Bit 3 Bit 2 Bit 5 Bit 1 Idle Phase being High Bit 4 Bit 3 Bit 2 Bit 5 Bit 6 Bit 4 Bit 3 Bit 2 Bit 5 Bit 6 Phase being High COP8SAx7 MICROCONTROLLER Bit 0 Bit 7 Out (LSB) (MSB) Bit 0 Bit 7 In (LSB) (MSB) Bit 0 Bit 1 (LSB) Bit 0 Bit 1 (LSB) 2-51 ...
Page 90
... All RAM, ports and registers (except A and PC) are mapped into data memory address space. RAM Select 64 On-chip RAM Bytes. Selected by ECON Register 128 On-chip RAM Bytes. 2-52 COP8SAx7 MICROCONTROLLER Address ADD REG On-chip RAM (48 Bytes Unused RAM (Reads as all ones On-chip RAM (112 Bytes) ...
Page 91
... MICROWIRE/PLUS Shift Register EA Timer T1 Lower Byte EB Timer T1 Upper Byte EC Timer T1 Autoload Register T1RA Lower Byte ED Timer T1 Autoload Register T1RA Upper Byte EE CNTRL Control Register EF PSW Register On-Chip RAM Mapped as Registers FC X Register FD SP Register FE B Register FF Segment Register COP8SAx7 MICROCONTROLLER Contents 2-53 ...
Page 92
... Several different operand addressing modes are available, allowing memory locations to be specifi variety of ways. An instruction can specify an address directly by supplying the specific address, or indirectly by specifying a register pointer. The contents of the register (or in some cases, two registers) point to the desired memory 2-54 COP8SAx7 MICROCONTROLLER ...
Page 93
... Example: Exchange Memory with Accumulator, B Indirect X A,[B] Reg/Data Memory Accumulator Memory Location 0005 Hex B Pointer Contents Contents Before After XX Hex A6 Hex A6 Hex A6 Hex Contents Contents Before After 01 Hex 87 Hex 87 Hex 01 Hex 05 Hex 05 Hex COP8SAx7 MICROCONTROLLER 2-55 ...
Page 94
... PCL) are used temporarily as a pointer to program memory. For purposes of accessing program memory, the contents of the Accumulator and PCL are exchanged. The data pointed to by the Program Counter is loaded into the Accumulator, and 2-56 COP8SAx7 MICROCONTROLLER Contents Before 03 Hex 62 Hex ...
Page 95
... The transfer-of-control addressing modes are described below. Each description includes an example of a Jump instruction using a particular addressing mode, and the effect on the Program Counter bytes of executing that instruction. Contents Contents Before After 04 Hex 04 Hex 35 Hex 36 Hex 1F Hex 25 Hex 25 Hex 25 Hex COP8SAx7 MICROCONTROLLER 2-57 ...
Page 96
... PCU PCL Jump Absolute Long. In this 3-byte instruction, 15 bits of the instruction opcode specify the new contents of the Program Counter. Example: Jump Absolute Long JMP 03625 Reg/Memory PCU PCL 2-58 COP8SAx7 MICROCONTROLLER Contents After 02 Hex 0F Hex Contents Contents Before After 0C Hex 01 Hex ...
Page 97
... The VIS instruction is a special case of the Indirect Transfer of Control addressing mode, where the double-byte vector associated with the interrupt is transferred from adjacent addresses in program memory into the Program Counter in order to jump to the associated interrupt service routine. Contents Contents Before After 01 Hex 01 Hex C4 Hex 32 Hex 26 Hex 26 Hex 32 Hex 32 Hex COP8SAx7 MICROCONTROLLER 2-59 ...
Page 98
... Program Counter. Jump Relative (JP) Jump Absolute (JMP) Jump Absolute Long (JMPL) Jump Indirect (JID) Jump to Subroutine (JSR) Jump to Subroutine Long (JSRL) Return from Subroutine (RET) Return from Subroutine and Skip (RETSK) Return from Interrupt (RETI) 2-60 COP8SAx7 MICROCONTROLLER ...
Page 99
... Push Data onto Stack (PUSH) Pop Data off of Stack (POP) Memory Bit Manipulation Instructions The memory bit manipulation instructions allow the user to set and reset individual bits in memory. Set Bit (SBIT) Reset Bit (RBIT) Reset Pending Bit (RPND) COP8SAx7 MICROCONTROLLER 2-61 ...
Page 100
... Instruction syntax with operand field descriptor • Full instruction description • Register level instruction description • Number of instruction cycles (each cycle equal to one microsecond at full clock speed) • Number of bytes ( instruction • Hexadecimal code for the instruction bytes 2-62 COP8SAx7 MICROCONTROLLER ...
Page 101
... RBIT #, [B] SP Stack Pointer, located in RAM register memory location 00FD pointer, located in RAM register memory location 00FC. [X] Contents of RAM data memory location indicated by the X pointer. [X+] Same as [X], except that the X pointer is post-incremented. [X-] Same as [X], except that the X pointer is post-decremented. COP8SAx7 MICROCONTROLLER 2-63 ...
Page 102
... Similarly, the Half Carry flag is either set or reset, depending on the presence or absence of a carry from the low-order nibble. Operation: A < VALUE + C C <- CARRY; HC <- HALF CARRY Instruction Addressing Mode ADC A,[B] Register Indirect (B Pointer) ADC A,# Immediate ADC A,MD Memory Direct 2-64 COP8SAx7 MICROCONTROLLER Instruction Bytes Hex Op Code Cycle 90/Imm # BD/MA/80 ...
Page 103
... The Carry and Half Carry flags are not changed. Operation: A < VALUE Instruction Addressing Mode ADD A,[B] Register Indirect (B Pointer) ADD A,MD Memory Direct ADD A,# Immediate Instruction Bytes Hex Op Code Cycles BD/MA/ 94/Imm.# COP8SAx7 MICROCONTROLLER 84 2-65 ...
Page 104
... The result is placed back in the accumulator. Operation: A <- A AND VALUE Instruction Addressing Mode AND A,[B] Register Indirect (B Pointer) AND A,# Immediate AND A,MD Memory Direct 2-66 COP8SAx7 MICROCONTROLLER Instruction Bytes Hex Op Code Cycles 95/Imm BD/MA/85 85 ...
Page 105
... This instruction may be used in testing for the pres- ence of any selected bits in the accumulator. The mask in the second byte is used to select which bits are tested. Operation AND #) = 0, THEN SKIP NEXT INSTRUCTION Instruction Addressing Mode ANDSZ A,# Immediate Instruction Bytes Hex Op Code Cycle 2 2 60/Imm.# COP8SAx7 MICROCONTROLLER 2-67 ...
Page 106
... Syntax: CLR A Description: The accumulator is cleared to all zeros. Operation: A <- 0 Instruction Addressing Mode CLR A Implicit 2-68 COP8SAx7 MICROCONTROLLER Instruction Bytes Hex Op Code Cycle ...
Page 107
... BCD (Binary Coded Decimal) format and produces the result in the same BCD format. The Carry and Half Carry flags remain un- changed. Operation: A (BCD FORMAT) <- A (BINARY FORMAT) Instruction Addressing Mode DCOR A Implicit Instruction Bytes Hex Op Code Cycles 1 1 COP8SAx7 MICROCONTROLLER 66 2-69 ...
Page 108
... Syntax: DECA Description: This instruction decrements the contents of the accumulator and places the result back in the accumulator. The Carry and Half Carry flags re- main unchanged. Operation: A < Instruction Addressing Mode DEC A Implicit 2-70 COP8SAx7 MICROCONTROLLER Instruction Bytes Hex Op Code Cycles ...
Page 109
... JP instruction is skipped as the program branches (skips) out of the loop. Operation: REG <- REG - 1 IF (REG - THEN SKIP NEXT INSTRUCTION Instruction Addressing Mode DRSZ REG# Register Direct (Implicit) Instruction Bytes Hex Op Code Cycles (REG#) COP8SAx7 MICROCONTROLLER 2-71 ...
Page 110
... IFBIT 1,A equivalent to ANDSZ A,#2 IFBIT 2,A equivalent to ANDSZ A,#4 IFBIT 3,A equivalent to ANDSZ A,#8 IFBIT 4,A equivalent to ANDSZ A,#16 IFBIT 5,A equivalent to ANDSZ A,#32 IFBIT 6,A equivalent to ANDSZ A,#64 IFBIT 7,A equivalent to ANDSZ A,#128 2-72 COP8SAx7 MICROCONTROLLER Instruction Bytes Hex Op Code Cycle ...
Page 111
... JP instruction is skipped as the program branches (skips) out of the loop. Operation POINTER LOW-ORDER NIBBLE EQUALS #, THEN SKIP NEXT INSTRUCTION Instruction Addressing Mode IFBNE # Implicit Instruction Bytes Hex Op Code Cycles 1 1 COP8SAx7 MICROCONTROLLER 4# 2-73 ...
Page 112
... IFC Description: The next Instruction is executed if the Carry flag is found set. Otherwise, the next instruction is skipped. The Carry flag is left unchanged. Operation CARRY (C = 0), THEN SKIP NEXT INSTRUCTION Instruction Addressing Mode IFC Implicit 2-74 COP8SAx7 MICROCONTROLLER Instruction Bytes Hex Op Code Cycles ...
Page 113
... Otherwise, the next instruction is skipped. Operation: IF CONTENTS OF SPECIFIED LOCATION THEN SKIP NEXT INSTRUCTION Instruction Addressing Mode IFEQ A,[B] Register Indirect (B Pointer) IFEQ A,# Immediate IFEQ A,MD Memory Direct IFEQ MD,# Memory Direct, Immediate VALUE Instruction Bytes Hex Op Code Cycles 92/Imm BD/MA/ A9/MA/Imm.# COP8SAx7 MICROCONTROLLER 82 2-75 ...
Page 114
... A successful greater than test results in the execution of the next in- struction. Otherwise, the next instruction is skipped. Operation VALUE THEN SKIP NEXT INSTRUCTION Instruction Addressing Mode IFGT A,[B] Register Indirect (B Pointer) IFGT A,# Immediate IFGT A,MD Memory Direct 2-76 COP8SAx7 MICROCONTROLLER Instruction Bytes Hex Op Code Cycles 93/Imm BD/MA/83 83 ...
Page 115
... The next instruction is executed if the Carry flag is found reset. Other- wise, the next instruction is skipped. The Carry flag is left unchanged. Operation: IF CARRY (C=1), THEN SKIP NEXT INSTRUCTION Instruction Addressing Mode IFNC Implicit Instruction Bytes Hex Op Code Cycles 1 1 COP8SAx7 MICROCONTROLLER 89 2-77 ...
Page 116
... A successful inequality comparison results in the execution of the next instruction; otherwise, the next instruction is skipped. Operation VALUE THEN SKIP NEXT INSTRUCTION Instruction Addressing Mode IFNE A,[B] Register Indirect (B Pointer) IFNE A,# Immediate IFNE A,MD Memory Direct 2-78 COP8SAx7 MICROCONTROLLER Instruction Bytes Hex Op Code Cycles 99/Imm BD/MA/B9 B9 ...
Page 117
... Syntax: INC A Description: This instruction increments the contents of the accumulator and places the result back in the accumulator. The Carry and Half Carry flags re- main unchanged. Operation: A < Instruction Addressing Mode INC A Implicit Instruction Bytes Hex Op Code Cycles 1 1 COP8SAx7 MICROCONTROLLER 8A 2-79 ...
Page 118
... FFFF Hex, which in turn will read all zeros and once again invoke the software trap INTR instruction. Operation: [SP] <- PCL [ <- PCU [ SET UP FOR NEXT STACK REFERENCE PC <- 0FF Instruction Addressing Mode INTR Implicit 2-80 COP8SAx7 MICROCONTROLLER Instruction Bytes Hex Op Code Cycles ...
Page 119
... Operation: PCL <- A PCL <- Program Memory (PCU,A) Instruction Addressing Mode JID Indirect Instruction Bytes Hex Op Code Cycles 3 1 COP8SAx7 MICROCONTROLLER A5 2-81 ...
Page 120
... If instruction byte segment 1, the jump address is in segment 1. Operation: PC11-8 <- HIADDR (HIGH NIBBLE OF SECOND BYTE OF INSTRUC- TION, LOW NIBBLE OF FIRST BYTE OF INSTRUCTION) PC7-0 <- LOADDR (SECOND BYTE OF INSTRUCTION) Addressing Instruction Mode JMP ADDR Absolute 2-82 COP8SAx7 MICROCONTROLLER 0FFF 1000 JMP SPANS TO NEXT SEGMENT Instruction Bytes Cycles 3 ...
Page 121
... PC) respectively. The program then jumps to the pro- gram memory location accessed by PC. Operation: PC14-8 <- HIADDR (SECOND BYTE OF INSTRUCTION) PC7-0 <- LOADDR (THIRD BYTE OF INSTRUCTION) Instruction Addressing Mode JMPL ADDR Absolute Instruction Bytes Cycles 4 3 COP8SAx7 MICROCONTROLLER Hex Op Code AC/HIADDR/ LOADDR 2-83 ...
Page 122
... A branch for- ward not allowed, since this zero opcode conflicts with the INTR software trap instruction. Operation: PC < DISP + 1 (DISP Instruction Addressing Mode JP DISP Relative 2-84 COP8SAx7 MICROCONTROLLER 0) Instruction Bytes Cycles DISP # Hex Op Code ...
Page 123
... PC11-8 <- HIADDR (HIGH NIBBLE OF RETURN ADDRESS, LOW NIBBLE OF FIRST BYTE INSTRUCTION) PC7-0 <- LOADDR (SECOND BYTE OF INSTRUCTION) Instruction Addressing Mode JSR ADDR Absolute 0FFE 0FFF 1000 3x xx ... 3x xx RETURN TO NEXT SEGMENT Instruction Bytes Cycles 5 2 COP8SAx7 MICROCONTROLLER 1FFF 1xxx Hex Op Code 3HIADDR/LOADDR 2-85 ...
Page 124
... PC. Operation: [SP] <- PCL [ <- PCU [SP - 2]: SET UP FOR NEXT STACK REFERENCE PC14-8 <- HIADDR (SECOND BYTE OF INSTRUCTION) PC7-0 <- LOADDR (THIRD BYTE OF INSTRUCTION) Instruction Addressing Mode JSRL ADDR Absolute 2-86 COP8SAx7 MICROCONTROLLER Instruction Bytes Cycles 5 3 Hex Op Code AD/HIADDR/ LOADDR ...
Page 125
... Consequently, in this instance, the fixed data table must reside in the next page of 256 bytes in the program memory. Operation: A <- Program Memory (PCU, A) Instruction Addressing Mode LAID Indirect Instruction Bytes Hex Op Code Cycles 3 1 COP8SAx7 MICROCONTROLLER A4 2-87 ...
Page 126
... The contents of the data memory location referenced by the X pointer are loaded into the accumulator, and then the X pointer is post-incremented. h) The contents of the data memory location referenced by the X pointer are loaded into the accumulator, and then the X pointer is post-decremented. 2-88 COP8SAx7 MICROCONTROLLER ...
Page 127
... Incrementing B Pointer LD A,[B-] Register Indirect With Post- Decrementing B Pointer LD A,# Immediate LD A,MD Memory Direct LD A,[X] Register Indirect (X Pointer) LD A,[X+] Register Indirect With Post- Incrementing X Pointer LD A,[X-] Register Indirect With Post- Decrementing X Pointer Instruction Bytes Hex Op Code Cycles 98/Imm 9D/ COP8SAx7 MICROCONTROLLER 2-89 ...
Page 128
... The immediate value found in the second byte of the instruction is transferred to the B pointer register. Operation: a) B3-B0 <- # and B7-B4 < <- # Instruction Addressing Mode LD B,# Short Immediate LD B,# Immediate 2-90 COP8SAx7 MICROCONTROLLER Instruction Bytes Hex Op Code Cycles 1 1 5(15-#) 2 2 9F/Imm.# ...
Page 129
... Operation: a)[B] <- # b)[B] < < c)[B] < < d)MD <- # Instruction Addressing Mode LD [B],# Register Indirect/Immediate LD [B+],# Register Indirect With Post- Incrementing/Immediate LD [B-],# Register Indirect With Post- Decrementing/Immediate LD MD,# Memory Direct/Immediate Instruction Bytes Hex Op Code Cycles 2 2 9E/Imm 9A/Imm 9B/Imm BC/MA/Imm.# COP8SAx7 MICROCONTROLLER 2-91 ...
Page 130
... The immediate value found in the second byte of the instruction is load- ed into the data memory register referenced by the low-order nibble of the first byte of the instruction. Operation: REG <- # Instruction Addressing Mode LD REG,# Implicit/Immediate 2-92 COP8SAx7 MICROCONTROLLER Instruction Bytes Hex Op Code Cycles 3 2 D(REG#)/ Imm.# ...
Page 131
... Syntax: NOP Description: No operation is performed by this instruction, so the net result is a delay of one instruction cycle time. Operation: NO OPERATION Instruction Addressing Mode NOP Implicit Instruction Bytes Hex Op Code Cycles 1 1 COP8SAx7 MICROCONTROLLER B8 2-93 ...
Page 132
... The result is placed back in the accumulator. Operation: A < VALUE Instruction Addressing Mode OR A,[B] Register Indirect (B Pointer) OR A,# Immediate OR A,MD Memory Direct 2-94 COP8SAx7 MICROCONTROLLER Instruction Bytes Hex Op Code Cycles 97/Imm BD/MA/87 87 ...
Page 133
... Syntax: POP A Description: The Stack Pointer (SP) is incremented, and then the contents of the data memory location referenced by the SP are transferred to the accumula- tor. Operation: SP < <- [SP] Instruction Addressing Mode POP Implicit Instruction Bytes Hex Op Code Cycles 3 1 COP8SAx7 MICROCONTROLLER 8C 2-95 ...
Page 134
... Syntax: PUSH A Description: The contents of the accumulator are transferred to the data memory lo- cation referenced by the Stack Pointer (SP), and then the SP is decre- mented. Operation: [SP] < < Instruction Addressing Mode PUSH Implicit 2-96 COP8SAx7 MICROCONTROLLER Instruction Bytes Hex Op Code Cycles ...
Page 135
... The selected bit (# = with 7 being the high-order bit) of the data memory location referenced by the a) B pointer is reset address in the second byte of the instruction is reset to 0. Operation: [Address:#] <- 0 Instruction Addressing Mode RBIT #,[B] Register Indirect (B Pointer) RBIT #,MD Memory Direct Instruction Bytes Hex Op Code Cycles BD/MA/6(8+#) COP8SAx7 MICROCONTROLLER 2-97 ...
Page 136
... Syntax: RC Description: Both the Carry and Half Carry flags are reset to 0. Operation: C < <- 0 Instruction Addressing Mode RC Implicit 2-98 COP8SAx7 MICROCONTROLLER Instruction Bytes Hex Op Code Cycles ...
Page 137
... PC). The return address has now been retrieved from the soft- ware stack in data memory RAM. The program now jumps to the program memory location accessed by PC. Operation: PCU <- [ PCL < SET UP FOR NEXT STACK REFERENCE Instruction Addressing Mode RET Implicit Instruction Bytes Hex Op Code Cycles 5 1 COP8SAx7 MICROCONTROLLER 8E 2-99 ...
Page 138
... RAM. The program now jumps to the program memory location accessed by PC. The Global Interrupt Enable flag (GIE) is set to 1. Operation: PCU <- [ PCL < SET UP FOR NEXT STACK REFERENCE GIE <- 1 Instruction Addressing Mode RETI Implicit 2-100 COP8SAx7 MICROCONTROLLER Instruction Bytes Hex Op Code Cycles ...
Page 139
... RAM. The program now jumps to and then skips the instruction in the program memory location accessed by PC. Operation: PCU <- [ PCL < SET UP FOR NEXT STACK REFERENCE SKIP NEXT INSTRUCTION Instruction Addressing Mode RETSK Implicit Instruction Bytes Hex Op Code Cycles 5 1 COP8SAx7 MICROCONTROLLER 8D 2-101 ...
Page 140
... Carry flag. The A3 (high-order bit of the low- order nibble) of the accumulator is transferred into the Half Carry flag (HC) as well as into the A4 bit position. Operation: C <- A7 <- A6 <- A5 <- A4 <- A3 <- A2 <- A1 <- A0 < <- A3 Instruction Addressing Mode RLC A Implicit 2-102 COP8SAx7 MICROCONTROLLER Instruction Bytes Hex Op Code Cycles ...
Page 141
... Software Trap Pending flag was not found set. Also, RPND unconditionally resets the Software Trap Pending flag (STPND). Operation: IF NMI interrupt acknowledged and STPND = 0 THEN NMPND <- 0 and STPND <- 0 ELSE STPND <- 0 Instruction Addressing Mode RPND Implicit Instruction Bytes Hex Op Code Cycles 1 1 COP8SAx7 MICROCONTROLLER B5 2-103 ...
Page 142
... The low-order accumulator bit (A0) is transferred to both the Carry flag and the Half Carry flag. Operation: C -> A7 -> A6 -> A5 -> A4 -> A3 -> A2 -> A1 -> A0 -> -> HC Instruction Addressing Mode RRC A Implicit 2-104 COP8SAx7 MICROCONTROLLER Instruction Bytes Hex Op Code Cycles ...
Page 143
... The selected bit (# = with 7 being the high-order bit) of the data memory location referenced by the a) B pointer is set address in the second byte of the instruction is set to 1. Operation: [Address:#] <- 1 Instruction Addressing Mode SBIT #,[B] Register Indirect (B Pointer) SBIT #,MD Memory Direct Instruction Bytes Hex Op Code Cycles BD/MA/7(8+#) COP8SAx7 MICROCONTROLLER 2-105 ...
Page 144
... Syntax: SC Description: Both the Carry and Half Carry flags are set to 1. Operation: C < <- 1 Instruction Addressing Mode SC Implicit 2-106 COP8SAx7 MICROCONTROLLER Instruction Bytes Hex Op Code Cycles ...
Page 145
... Operation: A < VALUE + C C <- ABSENCE OF BYTE BORROW HC <- ABSENCE OF LOW NIBBLE HALF BORROW Instruction Addressing Mode SUBC A,[B] Register Indirect (B Pointer) SUBC A,# Immediate SUBC A,MD Memory Direct Instruction Bytes Hex Op Code Cycles 91/Imm BD/MA/81 COP8SAx7 MICROCONTROLLER 81 2-107 ...
Page 146
... Syntax: SWAP A Description: The upper and lower nibbles of the accumulator are exchanged. Operation: A(7-4) <--> A Instruction Addressing Mode SWAP A Implicit 2-108 COP8SAx7 MICROCONTROLLER Instruction Bytes Hex Op Code Cycles ...
Page 147
... Hex with the VIS instruction at 00FF Hex). Operation: PCL <- VA (Interrupt Arbitration Vector generated by hardware) PCU <- Program Memory (PCU,VA) PCL <- Program Memory (PCU,VA+1) Instruction Addressing Mode VIS Implicit Instruction Bytes Hex Op Code Cycles 5 1 COP8SAx7 MICROCONTROLLER B4 2-109 ...
Page 148
... The contents of the data memory location referenced by the X pointer are exchanged with the contents of the accumulator, and then the X pointer is post-incremented. g) The contents of the data memory location referenced by the X pointer are exchanged with the contents of the accumulator, and then the X pointer is post-decremented. 2-110 COP8SAx7 MICROCONTROLLER ...
Page 149
... Register Indirect With Post- Incrementing B Pointer X A,[B-] Register Indirect With Post- Decrementing B Pointer X A,MD Memory Direct X A,[X] Register Indirect (X Pointer) X A,[X+] Register Indirect With Post- Incrementing X Pointer X A,[X-] Register Indirect With Post- Decrementing X Pointer Instruction Bytes Hex Op Code Cycles 9C/ COP8SAx7 MICROCONTROLLER 2-111 ...
Page 150
... The result is placed back in the accumulator. Operation: A <- A XOR VALUE Instruction Addressing Mode XOR A,[B] Register Indirect (B Pointer) XOR A,# Immediate XOR A,MD Memory Direct 2-112 COP8SAx7 MICROCONTROLLER Instruction Bytes Hex Op Code Cycles 96/Imm BD/MA/86 86 ...
Page 151
... Memory Indirectly Addressed by X Register MD Direct Addressed Memory Mem Direct Addressed Memory or [B] Meml Direct Addressed Memory or [B] or Immediate Data Imm 8-Bit Immediate Data Reg Register Memory: Addresses (Includes B, X and SP) Bit Bit Number ( Loaded with Exchanged with Registers Symbols COP8SAx7 MICROCONTROLLER 2-113 ...
Page 152
... JID Jump InDirect RET RETurn from subroutine RETSK RETurn and SKip RETI RETurn from Interrupt INTR Generate an Interrupt NOP No OPeration 2-114 COP8SAx7 MICROCONTROLLER Meml Meml + C, C Carry, HC Half Carry MemI + C, C Carry, HC Half Carry A A and Meml Skip next if (A and Imm ...
Page 153
... SUBC 1/1 3/4 2/2 AND 1/1 3/4 2/2 OR 1/1 3/4 2/2 XOR 1/1 3/4 2/2 IFEQ 1/1 3/4 2/2 IFGT 1/1 3/4 2/2 IFBNE 1/1 DRSZ 1/3 SBIT 1/1 3/4 RBIT 1/1 3/4 IFBIT 1/1 3/4 RPND 1/1 COP8SAx7 MICROCONTROLLER 2-115 ...
Page 154
... ANDSZ Memory Transfer Instructions Register Indirect [B] X A,* 1/1 LD A,* 1/1 LD B,Imm LD B,Imm LD Mem,Imm 2/2 LD Reg,Imm IFEQ MD,Imm * => Memory location addressed directly. 2-116 COP8SAx7 MICROCONTROLLER Transfer of Control Instructions 1/1 JMPL 1/1 JMP 1/1 JP 1/3 JSRL 1/1 JSR 1/1 JID 1/1 VIS 1/1 ...
Page 155
... LOWER NIBBLE COP8SAx7 MICROCONTROLLER 2-117 ...
Page 156
... Correct) instruction uses both the Cary and Half Carry flags as inputs but does not change the Carry and Half Carry flags. Also note that the #12 with the IFBNE 2-118 COP8SAx7 MICROCONTROLLER ;Define X-pointer as counter :Initialize B pointer ;Load mem with 0 and incr B pointer ...
Page 157
... A,[B] DCOR A X A,[B+] IFBNE #12 JP LOOP IFNC JP NEGRSLT ;Neg. result ( Borrow) ;No leading zero indicates decimal ;OverFLow if C ;Leading zero indicates hex ;Leading zero indicates hex ;Add hex 66 ;Decimal correct ;Overflow if C ;No leading zero indicates decimal ;Decimal correct COP8SAx7 MICROCONTROLLER 2-119 ...
Page 158
... A,[X+] ADD A,#066 ADC A,[B] DCOR A X A,[B+] IFBNE #4 JP LOOP IFC JP OVFLOW BCD SUBTRACTION LD B,#16 LD X,#24 SC LOOP: LD A,[X+] X A,[B] SUBC A,[B] DCOR A X A,[B+] IFBNE #4 JP LOOP IFNC JP NEGRSLT ;Neg. result ( Borrow) 2-120 COP8SAx7 MICROCONTROLLER ;Overflow if C ;Overflow if C ...
Page 159
... ROM pointer, If not equal to zero ;then repeat the loop ;else set the carry flag ;Load B pointer with 2 (point to TOTLO) ;Load accumulator with subtrahend ;Reverse operands for subtraction ;Subtract ;Increment minuend pointer ;If B pointer not equal to 4 ;then repeat the loop ;else return COP8SAx7 MICROCONTROLLER 2-121 ...
Page 160
... The entire dividend and test window is then shifted up (left shifted) one bit position with the quotient following the dividend. Note that the four left shifts (LD, ADC the LSHFT section of the program are repeated as straight-line code rather than a loop in order to optimize throughput time. 2-122 COP8SAx7 MICROCONTROLLER ...
Page 161
... When this case occurs, the TSUBT test subtract shows the divisor to be larger than the shifted dividend and no real subtraction occurs. Consequently, the high-order bit of the shifted dividend is again left shifted and results in a high-order carry. This test is illustrated in the following program for a 24-by-8-bit binary division. COP8SAx7 MICROCONTROLLER 2-123 ...
Page 162
... B,#3 LD [B],#0 LSHFT B,#0 LUP: LD A,[B] ADC A,[B] X A,[B+] IFBNE #4 JP LUP IFC JP SUBT TSUBT B,#3 LD A,[B+] SUBC A,[B] IFNC JP TEST SUBT: LD A,[B-] X A,[B] SUBC A,[B] X A,[B] LD B,#0 SBIT 0,[B] TEST: DRSZ CNTR JMP LSHFT RET 2-124 COP8SAx7 MICROCONTROLLER ...
Page 163
... CKI = 0 MHz CC = 5.5V 4. 5.5V – 5.5V – 0. 4.5V 3.3V –0 2.7V 1.8V –0 4.5V 1. 2.7V 0. 4.5V 2.7V – 2.7V 1.8V –2 COP8SAx7 MICROCONTROLLER Typ Max Units 5 0 2.1 mA < 1 1.0 2 –250 –110 A –33 A 2-125 ...
Page 164
... Sink (Push-Pull Mode) Allowable Sink Current per Pin (Note 6) D Outputs and All others Maximum Input Current without Latchup (Note 4) RAM Retention Voltage, Vr rise time from a 2. Input Capacitance Load Capacitance on D2 2-126 COP8SAx7 MICROCONTROLLER Conditions Min V = 4.5V 3.3V –0 2.7V 1.8V –0 ...
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... CC 4.5V V 5.5V CC 2.7V V < 4. 2.2k 100 4.5V V 5.5V CC 2.7V V < 4.5V CC 4.5V V 5.5V CC 2.7V V < 4. (the pins do not have source current when biased at a voltage below V CC COP8SAx7 MICROCONTROLLER Min Typ Max Units 1 2 2.0 s TBD TBD % 200 ns 500 150 ns 0 ...
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... G and L Port Input Hysteresis Output Current Levels D Outputs Source Sink L Port Source (Weak Pull-Up) Source (Push-Pull Mode) Sink (L0-L3, Push-Pull Mode) Sink (L4-L7, Push-Pull Mode) 2-128 COP8SAx7 MICROCONTROLLER 7V –0. +0.6V CC 2KV (Human Body Model 100 mA –65˚C to +140˚C TA +85˚C unless otherwise ...
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... Input Capacitance Load Capacitance on D2 Conditions Min V = 2.7V 0.4V 0 4.5V 2.7V –10 2.7V 1.8V –2 4.5V 3.3V –0 2.7V 1.8V –0 4.5V 0.4V 1 2.7V 0.4V 0 2.0 1.2 (Note 6) (Note 6) COP8SAx7 MICROCONTROLLER Typ Max Units mA –110 A – 200 1000 pF 2-129 ...
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... WARNING: Voltages in excess of 14 volts will cause damage to the pins. This warning excludes ESD transients. Note 5: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs. Note 6: Parameter characterized but not tested. 2-130 COP8SAx7 MICROCONTROLLER ( –40˚C T ...
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... 5.5V – 5.5V – 0. 4.5V 3.3V –0 4.5V 1. 4.5V 2.7V –9 4.5V 3.3V –0 9 4.5V 1. 4.5V 0.4V 1 4.5V 2.7V –9 4.5V 3.3V –0 4.5V 0.4V 1 COP8SAx7 MICROCONTROLLER Uni Typ Max 6.0 mA < 1.0 2 –400 –140 –140 2-131 ...
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... Allowable Sink Current per Pin (Note 6) D Outputs and All others Maximum Input Current without Latchup (Note 4) RAM Retention Voltage, Vr rise time from a 2. Input Capacitance Load Capacitance on D2 2-132 COP8SAx7 MICROCONTROLLER Conditions Min 2.0 1.2 (Note 6) (Note 6) Uni Typ Max ...
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... MHz Ext Clock MHz Ext Clock 4.5V V 5.5V CC 4. 2.2k 100 4.5V V 5.5V CC 4. (the pins do not have source current when biased at a voltage below UWS t UWH COP8SAx7 MICROCONTROLLER Min Typ Max Units 1 2.0 s TBD % 200 0 220 ...
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... National’s patent ESD protection and EMI reduction circuits are implemented on device to address ESD/EMI problems. 2.22 INPUT PROTECTION The COP8SAx7 input pins have internal circuitry for protection from ESD. The internal circuitry is shown in Figure 2-31. Figure 2-31 Ports L/C/G/F Input Protection (Except G6) The input protection circuitry is implemented with the P_channel transistors ...
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... V contains only resistor which is connected between the V GND return line PROTECTION INPUT PROTECTION GND Figure 2-33 On-Chip ESD Detection/Protection Circuit between ESD events. The Merrill Resistor block CC DIODE 4M DIODE COP8SAx7 MICROCONTROLLER and GND CC supply line and the CC DETECTOR 2-135 CC ...
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... This is the noise which is coupled to the output through V and GND. Another point to keep in mind is that rarely does one single output switch “FACT Advanced CMOS Logic Databook”, National Semiconductor, 1993 2-136 COP8SAx7 MICROCONTROLLER -to-GND loops or output-to-GND loops – Freq ...
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... Curren |E| Max |E| Max t ( V/M) (mA) M) 37.56 8.3 18.4 3.66 0.3 -10.2 26.13 44.2 33.0 4.44 0.6 -4.4 16.82 80.2 38.1 4.71 2.0 6.0 11.21 104.0 40.4 4.86 5.8 15.2 7.82 127.4 42.1 COP8SAx7 MICROCONTROLLER CC traces should be CC 2-137 ...
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... The use of inductive decoupling, which will increase the series impedance of the power supply, appears to be contradictory to the effect of capacitive decoupling. However, the 2-138 COP8SAx7 MICROCONTROLLER and GND planes provide additional CC CC ...
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... It is much better to design the system with the control of emissions in mind from the start rather than to apply bandages when it is time to begin production. which may be present during CC COP8SAx7 MICROCONTROLLER 2-139 ...
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... EMI issues influencing embedded control designs. National has achieved 15-20 dB reduction in EMI transmissions when designs have incorporated its patented EMI reducing circuitry (Figure 2-34). COP8SAx7 Device Without EMI Improvements COP8SAx7 Device With EMI Improvements 2-140 COP8SAx7 MICROCONTROLLER products ...
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... The best way to determine the values which will work well for a particular application is by experimentation. voltage swings were confined DGND when both the pull up and the pull CC (Driver (Logic and COP8SAx7 MICROCONTROLLER voltage CC than the perimeter. ),V (a global bonded to the same pin, CC pad is not bonded. 2-141 ...
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... Pin GND GND Pin DGND Figure 2-35 Block diagram of EMI Circuitry 2-142 COP8SAx7 MICROCONTROLLER Choke Clock Device Oscillator Chip Nucleus Level Logic Shifting CKI CKO Gradual Turn On OUTPUT Input INPUT Buffer ...
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SUMMARY • iceMASTER: IM-COP8/400 -- Full featured in-circuit emulation for all COP8 prod- ucts. A full set of COP8 Basic and Feature Family device and package specific probes are available. • COP8 Debug Module: Moderate-cost in-circuit emulation and development ...
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Figure 3-1 COP8 iceMASTER Environment • Full 4k frame synchronous trace memory. Address, instruction, and eight unspec- ified, circuit connectable trace lines. Display can be high-level language source (e.g., C source), assembly, or mixed. • A full 64k hardware configurable ...
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... Optional Surface Mount Adapter Kits MHW-COP8/44P-Q MHW-SOIC-28 MHW-SOIC-20 MHW-SOIC-16 e.g., Target package is 44P; order: IM-COP8/400-1, COP8SA-IM44V and MHW-COP8/44V-P. 3.3 iceMASTER DEBUG MODULE (DM) The iceMASTER Debug Module based, combination in-circuit emulation tool and COP8 based OTP/EPROM programming tool developed and marketed by MetaLink Corporation to support the whole COP8 family of products ...
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COP8 microcontroller and in addition serves as a programming tool for COP8 OTP and EPROM product families. It offers the following features: • Real-time in-circuit emulation; full operating voltage range operation, full DC- ...
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... COP8SA-DM Cable Adapters, requires one for emulation DM-COP8/44P DM-COP8/40D DM-COP8/28D DM-COP8/20D DM-COP8/16D Optional Surface Mount Adapter Kits MHW-COP8/44P-Q DM-COP8/28D-SO DM-COP8/20D-SO DM-COP8/16D-SO Optional Programming Adapters COP8-PGMA-44Q 3.4 iceMASTER EVALUATION PROGRAMMING UNIT (EPU) The iceMASTER-COP8 EPU based, in-circuit simulation tool to support the feature family COP8 products. ...
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In addition, the EPU has programming capability, with added adapters, for programming the whole COP8 product family of OTP and EPROM products. The product includes the following features: • Non-real-time in-circuit simulation. Program overlay memory is PC resident; in- ...
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Installing the EPU Software You must have at least 1700 kilobytes of free disk space on your PC to install the EPU host software. To install this software type the following from the DOS command line: C:\>a:\install a: c: \epu-cop8 ...
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... Ensure that the jumper block is NOT installed on the EPU board this conditions the programming socket pins for the COP8SAx algorithm. The sample devices shipped with the EPU are 40-pin DIP packages; the EPU will program all COP8SAx DIP packages, directly. Other packages require a programming adaptor. To enable the programming algorithm, start the EPU software and select the MISC menu box ...
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COP8-DEV-IBMA Assembler SDK on installable 3.5” PC format. Periodic upgrades and most recent version is available on National’s BBS and the Internet. 3.6 COP8 C COMPILER A C Compiler is developed and marketed by Byte Craft Limited. The COP8C compiler ...
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North/South Manufacturer America BP Microsystems US: Houston, TX (USA) 800-225-2102 www.bpmicro.com 713-688-4600 sales@bpmicro.com fax: 713-688-0920 bbx: 713-688-9283 Data I/O US: Redmond, WA (USA) 800-426-1045 www.data-io.com 206-881-6444 sales@data-io.com fax: 206-882-1043 techhelp@data-io.com bbs: 206-882-3211 CAN: 905-678-0761 fax: 905-678-7306 US: ...
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North/South Manufacturer America Systems General US: Milpitas, CA (Taiwan) 800-967-4776 408-263-6667 fax: 408-262-9220 bbs: 408-262-6438 Xeltek US: Sunnyvale, CA (USA) 408-524-1929 www.xeltek.com fax: 408-245-7084 info@xeltek.com bbs: 408-245-7082 3.8 AVAILABLE LITERATURE For more information, please see the COP8 Basic Family User's ...
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... Dial-A-Helper via a WorldWide Web Browser ftp://nscmicro.nsc.com 3.11 NATIONAL SEMICONDUCTOR ON THE WORLDWIDE WEB See us on the WorldWide Web at: http://www.national.com 3.12 CUSTOMER RESPONSE CENTER Complete product information and technical support is available from National's customer response centers. Please see back cover for telephone number in your area. ...
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... This chapter describes several application examples using the COP8SAx7 family of microcontrollers. Design examples often include block diagrams and/or assembly code. Certain hardware design considerations are also presented. Topics covered in this chapter include the following: TESTING A REMOTE NORMALLY OPEN SWITCH FOR CONNECTION ...
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... Usually this requires a linear device such as an additional transistor. If the switch is connected, a programmable I/O port on a microcontroller that can be placed in the TRI-STATE mode can detect the presence of the 10k resistor without additional parts. The following shows an example of this technique using a COP8SAx7. 10K1 SET PIN HIGH ...
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... IFBIT 0, GPINS JP OPEN NORM: NOP SBIT 0, DPORT RBIT 1, DPORT JP CHECK OPEN: NOP RBIT 0, DPORT SBIT 1, DPORT JP CHECK ; Set G0 High ; Test G0. High? ; Yes ; No, close switch ; Configure G0 as input with weak pullup ; Test Go. High? ; Yes J1 disconnected ; No, open switch COP8SAx7 APPLICATION IDEAS 4-3 ...
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... The master initiates data transfer on the MICROWIRE interface by turning on the SK clock series of data transfers takes place between the master and slave devices. 5. The master pulls the CS line high to end the MICROWIRE operation. The slave device returns to normal mode of operation. 4-4 COP8SAx7 APPLICATION IDEAS ...
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... Figure 4-3) as agreed upon in the protocol. 4.2.2 NM93C06-COP8SAx7 Interface This example shows the COP8SAx7 interface to a NM93C06, a 256-bit E the MICROWIRE/PLUS interface. The pin connections for the interface is shown in Figure 4-4. Some notes on the NM93C06 interface requirements are: 1. The SK clock frequency should be less than 250 KHz. The SK clock should be confi ...
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... All commands and data are shifted in/out on the rising edge of the SK clock. All instructions are initiated by a low-to-high transition on CS followed by a low-to-high transition on DI. A detailed explanation of the NMC93C06 E considerations can be found in the data sheet. A source listing of the software used to interface the NM93C06 with the COP8SAx7 is provided below. 4-6 COP8SAx7 APPLICATION IDEAS Address 1 0000 A3A2A1A0 Read Register 0– ...
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... NMC93C06 register ;03Write to NMC93C06 register ;OthersIllegal combination ;Delay counter register ;Delay counter register ;select standard SK mode ;Initialize G data reg to zero ;Enable MSEL, select MW rate of 2tc COP8SAx7 APPLICATION IDEAS 4-7 ...
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... A,RDATL RBIT 0,PORTGD RET ; WR494: LD A,WDATH 4-8 COP8SAx7 APPLICATION IDEAS ;Set chip select high ;Load SIOR with start bit ;Send out the start bit ;Load SIOR with command byte ;Send out command byte ;Any further processing? ;Yes ;No, reset CS and return ;Read or write? ...