C8051F000DK-H Silicon Laboratories Inc, C8051F000DK-H Datasheet - Page 74
C8051F000DK-H
Manufacturer Part Number
C8051F000DK-H
Description
DEV KIT FOR C8051F000/F001/F002
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051F005-TB.pdf
(171 pages)
Specifications of C8051F000DK-H
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- Current page: 74 of 171
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10.3.1. Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should
not be set to logic l. Future product versions may use these bits to implement new features in which case the reset
value of the bit will be logic 0, selecting the feature’s default state. Detailed descriptions of the remaining SFRs are
included in the sections of the datasheet associated with their corresponding system function.
Bits 7-0: SP: Stack Pointer.
Bits 7-0: DPL: Data Pointer Low.
Bits 7-0: DPH: Data Pointer High.
R/W
R/W
R/W
Bit7
Bit7
Bit7
The stack pointer holds the location of the top of the stack. The stack pointer is
incremented before every PUSH operation. The SP register defaults to 0x07 after reset.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed RAM and Flash Memory.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed RAM and Flash Memory.
R/W
R/W
R/W
Bit6
Bit6
Bit6
Figure 10.5. DPH: Data Pointer High Byte
Figure 10.4. DPL: Data Pointer Low Byte
R/W
R/W
R/W
Bit5
Bit5
Bit5
Figure 10.3. SP: Stack Pointer
R/W
R/W
R/W
Bit4
Bit4
Bit4
Rev. 1.7
R/W
R/W
R/W
Bit3
Bit3
Bit3
R/W
R/W
R/W
Bit2
Bit2
Bit2
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
R/W
R/W
R/W
Bit1
Bit1
Bit1
R/W
R/W
R/W
Bit0
Bit0
Bit0
SFR Address:
SFR Address:
SFR Address:
Reset Value
Reset Value
Reset Value
00000111
00000000
00000000
0x81
0x82
0x83
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