C8051F000DK-H Silicon Laboratories Inc, C8051F000DK-H Datasheet - Page 86
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C8051F000DK-H
Manufacturer Part Number
C8051F000DK-H
Description
DEV KIT FOR C8051F000/F001/F002
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051F005-TB.pdf
(171 pages)
Specifications of C8051F000DK-H
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- Current page: 86 of 171
- Download datasheet (2Mb)
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode. The
Missing Clock Detector should be disabled if the CPU is to be put to sleep for longer than the MCD timeout of
100sec.
Bit7:
Bits6-2: GF4-GF0: General Purpose Flags 4-0.
Bit1:
Bit0:
SMOD
R/W
Bit7
SMOD: Serial Port Baud Rate Doubler Enable.
0: Serial Port baud rate is that defined by Serial Port Mode in SCON.
1: Serial Port baud rate is double that defined by Serial Port Mode in SCON.
These are general purpose flags for use under software control.
Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0.
1: Goes into power down mode. (Turns off internal oscillator).
Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0.
1: Goes into idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, Serial
STOP: Stop Mode Select.
IDLE: Idle Mode Select.
Ports, and Analog Peripherals are still active.)
GF4
R/W
Bit6
Figure 10.15. PCON: Power Control Register
R/W
GF3
Bit5
R/W
GF2
Bit4
Rev. 1.7
GF1
R/W
Bit3
R/W
GF0
Bit2
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
STOP
R/W
Bit1
IDLE
R/W
Bit0
SFR Address:
Reset Value
00000000
0x87
86
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