M5249C3 Freescale Semiconductor, M5249C3 Datasheet - Page 8

• Manufacturer Part Number: M5249C3
• Description: KIT EVAL FOR M5249 W/ETHERNET
• Manufacturer: Freescale Semiconductor
• Series: ColdFire®r
• Type: Microprocessorr

Specifications of M5249C3

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MCF5249
• Interface Type: RS-232, Ethernet
• For Use With/related Products: MCF5249
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SCF5249 Functional Overview
Two internal audio channels and the dual UART can be used with the DMA channels. All channels can
perform memory to memory transfers. The DMA controller has a user-selectable, 24- or 16-bit counter and
a programmable DMA exception handler.
External requests are not supported.
5.3
The integrated EMAC unit provides a common set of DSP operations and enhances the integer multiply
instructions in the ColdFire architecture. The EMAC provides functionality in three related areas:
Multiplies of 16x16 and 32x32 with 48-bit accumulates are supported in addition to a full set of extensions
for signed and unsigned integers plus signed, fixed-point fractional input operands. The EMAC has a
single-clock issue for 32x32-bit multiplication instructions and implements a four-stage execution
pipeline.
5.4
The instruction cache improves system performance by providing cached instructions to the execution unit
in a single clock. The SCF5249 processor uses a 8K-byte, direct-mapped instruction cache to achieve 125
MIPS at 140 Mhz. The cache is accessed by physical addresses, where each 16-byte line consists of an
address tag and a valid bit. The instruction cache also includes a bursting interface for 16-bit and 8-bit port
sizes to quickly fill cache lines.
5.5
The 96-KByte on-chip SRAM is split over two banks, SRAM0 (32k) and SRAM1 (64K). It provides one
clock-cycle access for the ColdFire core. This SRAM can store processor stack and critical code or data
segments to maximize performance. Memory in the second bank can be accessed under DMA.
5.6
The SCF5249 DRAM controller provides a glueless interface for up to two banks of DRAM, each of which
can be up to 32 MBytes. The controller supports a 16-bit data bus. A unique addressing scheme allows for
increases in system memory size without rerouting address lines and rewiring boards. The controller
operates in page mode, non-page mode, and burst-page mode and supports SDRAMS.
5.7
The SCF5249 provides a glueless interface to 16-bit port size SRAM, ROM, and peripheral devices with
independent programmable control of the assertion and negation of chip-select and write-enable signals.
The SCF5249 also supports bursting ROMs.
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1. Faster signed and unsigned integer multiplies
2. New multiply-accumulate operations supporting signed and unsigned operands
3. New miscellaneous register operations
Enhanced Multiply and Accumulate Module (EMAC)
Instruction Cache
Internal 96-KByte SRAM
DRAM Controller
System Interface
SCF5249 Integrated ColdFire® Microprocessor Data Sheet, Rev. 3
Freescale Semiconductor