KIT33999EKEVB Freescale Semiconductor, KIT33999EKEVB Datasheet - Page 7

• Manufacturer Part Number: KIT33999EKEVB
• Description: KIT EVAL 33999 16OUTPUT SW W/SPI
• Manufacturer: Freescale Semiconductor

Specifications of KIT33999EKEVB

• Main Purpose: Power Management, Low Side Driver (Internal FET)
• Embedded: No
• Utilized Ic / Part: MC33999
• Primary Attributes: 16 Outputs, 5 ~ 27V, 900mA, SPI Interface, PWM Interface
• Secondary Attributes: 0.55 Ohm RdsON, Temperature, Over Voltage, Short Circuit Protection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 4. Dynamic Electrical Characteristics
noted. Typical values noted reflect the approximate parameter means at V
unless otherwise noted.
POWER OUTPUT TIMING
DIGITAL INTERFACE TIMING
Notes
Analog Integrated Circuit Device Data
Freescale Semiconductor
Output Slew Rate
Output Turn ON Delay Time
Output Turn OFF Delay Time
Output ON Short Fault Disable Report Delay
Output OFF Open Fault Delay Time
Output PWM Frequency
Required Low State Duration on V
Falling Edge of
Falling Edge of SCLK to Rising Edge of
SI to Falling Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to SI (Required Setup Time)
SI,
SI,
Time from Falling Edge of
Time from Rising Edge of
Time from Rising Edge of SCLK to SO Data Valid
15.
17.
18.
19.
20.
21.
22.
23.
16.
Characteristics noted under conditions 3.1 V ≤ SO
R
V
CS
CS
L
PWR
, SCLK Signal Rise Time
, SCLK Signal Fall Time
= 60 Ω
Output slew rate measured across a 60 Ω resistive load.
Output turn ON and OFF delay time measured from 50% rising edge of CS to 80% and 20% of initial voltage.
Duration of fault before fault bit is set. Duration between access times must be greater than 450 µs to read faults.
This parameter is guaranteed by design but is not production tested.
Rise and Fall time of incoming SI,
Time required for valid output status data to be available on SO pin.
Time required for output status data to be terminated at SO pin.
Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.
This parameter is guaranteed by design. Production test equipment used 4.16 MHz, 5.5 V/3.1 V SPI Interface.
≤ 0.2 V
(15)
CS
(18)
to Rising Edge of SCLK (Required Setup Time)
CS
CS
(16)
to SO High Impedance
(16)
to SO Low Impedance
(23)
(19)
Characteristic
(19)
PWR
(17)
for Reset
CS
DYNAMIC ELECTRICAL CHARACTERISTICS
CS
, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
(Required Setup Time)
(17)
(22)
(20)
(21)
PWR
≤ 5.25 V, 9.0 V ≤ V
T
T
T
DLY
T
T
DLY
T
Symbol
T
DLY
T
T
T
SI (
PWR
DLY
T
T
T
T
SO (
T
SO (
SI (
VALID
FREQ
LEAD
SR
(
R (SI)
LAG
F (SI)
PWR
HOLD
RST
SHORT)
(
OPEN
(
SU
DIS
(
OFF
EN
ON
= 13 V, T
)
)
≤ 16 V, -40°C ≤ T
)
)
)
)
)
DYNAMIC ELECTRICAL CHARACTERISTICS
Min
100
100
100
1.0
1.0
1.0
50
16
20
A
–
–
–
–
–
–
–
= 25°C under nominal conditions
ELECTRICAL CHARACTERISTICS
C
Typ
2.0
2.0
4.0
5.0
5.0
25
–
–
–
–
–
–
–
–
–
–
≤ 125°C unless otherwise
Max
450
450
2.0
10
10
10
10
50
50
80
–
–
–
–
–
–
V/
Unit
kHz
µ
µ
µ
µ
µ
ns
ns
ns
ns
ns
ns
ns
ns
ns
µ
33999
s
s
s
s
s
s
7