EVAL-ADT7475EB ON Semiconductor, EVAL-ADT7475EB Datasheet - Page 20

• Manufacturer Part Number: EVAL-ADT7475EB
• Description: BOARD EVALUATION FOR ADT7475
• Manufacturer: ON Semiconductor
• Series: dBCool®r
• Type: Temperature Sensorr

Specifications of EVAL-ADT7475EB

• Contents: Evaluation Board
• For Use With/related Products: ADT7475
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Generating SMBALERT Interrupts from A THERM
Timer Events
programmable THERM timer limit has been exceeded. This
allows the system designer to ignore brief, infrequent
THERM assertions, while capturing longer THERM timer
events. Register 0x7A is the THERM timer limit register.
This 8−bit register allows a limit from 0 seconds (first
THERM assertion) to 5.825 seconds to be set before an
SMBALERT is generated. The THERM timer value is
compared with the contents of the THERM timer limit
register.
Configuring the THERM Behavior
The ADT7475 can generate SMBALERTs when a
1. Configure the relevant pin as the THERM timer
2. Select the desired fan behavior for THERM timer
input. Setting Bit 1 (THERM) of Configuration
Register 3 (0x78) enables the THERM timer
monitoring functionality. This is disabled on Pin 9
by default.
Setting Bit 0 and Bit 1 (PIN9FUNC) of
Configuration Register 4 (0x7D) enables THERM
timer/output functionality on Pin 9 (Bit 1,
THERM, of Configuration Register 3, must also
be set). Pin 9 can also be used as TACH4.
events.
Assuming that the fans are running, setting Bit 2
(BOOST bit) of Configuration Register 3 (0x78)
causes all fans to run at 100% duty cycle whenever
THERM is asserted. This allows fail−safe system
cooling. If this bit is 0, the fans run at their current
settings and are not affected by THERM events. If
the fans are not already running when THERM is
asserted, the fans do not run to full speed.
(REGISTER 0x7A)
TIMER LIMIT
THERM
Figure 28. Functional Block Diagram of the ADT7475 THERM Monitoring Circuitry
728.32ms
364.16ms
182.08ms
91.04ms
45.52ms
22.76ms
2.914s
1.457s
0
1
2
3
4
5
6
COMPARATOR
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7
20
CLEARED
ON READ
7 6 5 4 3 2 1 0
limit value, then the F4P bit (Bit 5) of Interrupt Status
Register 2 is set, and an SMBALERT is generated. Note that
the F4P bit (Bit 5) of Interrupt Mask Register 2 (0x75) masks
out SMBALERTs if this bit is set to 1, although the F4P bit
of Interrupt Status Register 2 is still set if the THERM timer
limit is exceeded.
timer, limit, and associated circuitry. Writing a value of 0x00
to the THERM timer limit register (0x7A) causes
SMBALERT to be generated on the first THERM assertion. A
THERM timer limit value of 0x01 generates an SMBALERT
once cumulative THERM assertions exceed 45.52 ms.
IN
LATCH
RESET
If the THERM timer value exceeds the THERM timer
Figure 28 is a functional block diagram of the THERM
INTERRUPT MASK REGISTER 2
3. Select whether THERM timer events should
4. Select a suitable THERM limit value.
5. Select a THERM monitoring time.
OUT
generate SMBALERT interrupts.
Bit 5 (F4P) of Interrupt Mask Register 2 (0x75),
when set, masks out SMBALERTs when the
THERM timer limit value is exceeded. This bit
should be cleared if SMBALERTs based on
THERM events are required.
This value determines whether an SMBALERT is
generated on the first THERM assertion or only if
a cumulative THERM assertion time limit is
exceeded. A value of 0x00 causes an SMBALERT
to be generated on the first THERM assertion.
This value specifies how often OS− or BIOS−level
software checks the THERM timer. For example,
BIOS could read the THERM timer once an hour to
determine the cumulative THERM assertion time.
If, for example, the total THERM assertion time is
<22.76 ms in Hour 1, >182.08 ms in Hour 2, and
>2.914 s in Hour 3, this can indicate that system
1 = MASK
F4P BIT (BIT 5)
INTERRUPT STATUS
REGISTER 2
(REGISTER 0x75)
F4P BIT (BIT 5)
THERM TIMER CLEARED ON READ
1.457s
182.08ms
2.914s
728.32ms
364.16ms
91.04ms
45.52ms
22.76ms
(REGISTER 0x79)
THERM TIMER
SMBALERT
THERM