EVAL-ADT7475EB ON Semiconductor, EVAL-ADT7475EB Datasheet - Page 48

• Manufacturer Part Number: EVAL-ADT7475EB
• Description: BOARD EVALUATION FOR ADT7475
• Manufacturer: ON Semiconductor
• Series: dBCool®r
• Type: Temperature Sensorr

Specifications of EVAL-ADT7475EB

• Contents: Evaluation Board
• For Use With/related Products: ADT7475
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

1. Exceeding any of the TACH limit registers by 1 indicates that the fan is running too slowly or has stalled. The appropriate status bit is set
1. These registers become read−only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to these registers fail.
Table 24. Fan Tachometer Limit Registers
Table 25. Register 0x55 — TACH1 Minimum High Byte (Power−On Default = 0xFF)
Table 26. PWM Configuration Registers
Table 27. Register 0x05C, Register 0x5D, and Register 0x5E — PWM Configuration Registers
(Power−On Default = 0x62)
Bit No.
Bit No.
[4:0]
[7:5]
[2:0]
[7:5]
Register Address
Register Address
in Interrupt Status Register 2 to indicate the fan failure. Setting the Configuration Register 1 lock bit has no effect on these registers.
[4]
0x5A
0x5B
0x5C
0x5D
0x5E
0x54
0x55
0x56
0x57
0x58
0x59
Mnemonic
Mnemonic
Reserved
SCADC
BHVR
SPIN
INV
Read−only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TACH1 minimum low byte.
TACH1 minimum high byte/single−channel ADC channel select.
TACH2 minimum low byte.
TACH2 minimum high byte.
TACH3 minimum low byte.
TACH3 minimum high byte.
TACH4 minimum low byte.
TACH4 minimum high byte.
These bits are reserved when Bit 6 of Configuration Register 2 (0x73) is set (single−channel ADC
mode). Otherwise, these bits represent Bits [4:0] of the TACH1 minimum high byte register.
When Bit 6 of Configuration Register 2 (0x73) is set (single−channel ADC mode), these bits are
used to select the only channel from which the ADC makes measurements. Otherwise, these
bits represent Bits [7:5] of the TACH1 minimum high byte register.
PWM1 configuration.
PWM2 configuration.
PWM3 configuration.
These bits control the startup timeout for PWMx. The PWM output stays high until two valid
TACH rising edges are seen from the fan. If there is not a valid TACH signal during the fan
TACH measurement directly after the fan startup timeout period, the TACH measurement reads
0xFFFF and Interrupt Status Register 2 reflects the fan fault. If the TACH minimum high and low
bytes contain 0xFFFF or 0x0000, the Interrupt Status Register 2 bit is not set, even if the fan
has not started.
This bit inverts the PWM output. The default is 0, which corresponds to a logic high output for
100% duty cycle. Setting this bit to 1 inverts the PWM output so that 100% duty cycle
corresponds to a logic low output.
These bits assign each fan to a particular temperature sensor for localized cooling.
000 = No startup timeout
001 = 100 ms
010 = 250 ms (default)
011 = 400 ms
100 = 667 ms
101 = 1 sec
110 = 2 sec
111 = 4 sec
000 = Remote 1 temperature controls PWMx (automatic fan control mode).
001 = Local temperature controls PWMx (automatic fan control mode).
010 = Remote 2 temperature controls PWMx (automatic fan control mode).
011 = PWMx runs full speed.
100 = PWMx disabled (default).
101 = Fastest speed calculated by local and Remote 2 temperature controls PWMx.
110 = Fastest speed calculated by all three temperature channel controls PWMx.
111 = Manual Mode. PWM duty cycle registers (0x30 to 0x32) become writable.
(Note 1)
(Note 1)
http://onsemi.com
Description
Description
48
Description
Description
Power−On Default
Power−On Default
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x62
0x62
0x62