EVAL-ADT7475EB ON Semiconductor, EVAL-ADT7475EB Datasheet - Page 55

• Manufacturer Part Number: EVAL-ADT7475EB
• Description: BOARD EVALUATION FOR ADT7475
• Manufacturer: ON Semiconductor
• Series: dBCool®r
• Type: Temperature Sensorr

Specifications of EVAL-ADT7475EB

• Contents: Evaluation Board
• For Use With/related Products: ADT7475
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

1. If this register is read, this register and the registers holding the MSB of each reading are frozen until read.
1. These registers become read−only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to these registers fail.
Table 45. Register 0x77 — Extended Resolution Register 2
Table 46. Register 0x78 — Configuration Register 3 (Power−On Default = 0x00)
Table 47. Register 0x79 — THERM Timer Status Register (Power−On Default = 0x00)
Table 48. THERM Timer Limit Register (Power−On Default = 0x00)
Bit No.
Bit No.
Bit No.
Bit No.
[3:2]
[5:4]
[7:6]
[7:1]
[7:0]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
Mnemonic
Mnemonic
Mnemonic
Mnemonic
THERM
BOOST
ALERT
Enable
ASRT/
TDM1
TDM2
TMR0
LTMP
FAST
LIMT
TMR
DC1
DC2
DC3
DC4
Read−only
Read−only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Remote 1 temperature LSBs. Holds the 2 LSBs of the 10−bit Remote 1 temperature measurement.
Local temperature LSBs. Holds the 2 LSBs of the 10−bit local temperature measurement.
Remote 2 temperature LSBs. Holds the 2 LSBs of the 10−bit Remote 2 temperature measurement.
ALERT = 1, Pin 5 (PWM2/SMBALERT) is configured as an SMBALERT interrupt output to
indicate out−of−limit error conditions.
THERM Enable = 1 enables THERM timer monitoring functionality on Pin 9. Also determined by
Bit 0 and Bit 1 (PIN9FUNC) of Configuration Register 4. When THERM is asserted, if the fans
are running and the boost bit is set, the fans run at full speed. Alternatively, THERM can be
programmed so that a timer is triggered to time how long THERM has been asserted.
When THERM is an input and BOOST = 1, assertion of THERM causes all fans to run at the
maximum programmed duty cycle for fail−safe cooling.
FAST = 1, enables fast TACH measurements on all channels. This increases the TACH
measurement rate from once per second to once every 250 ms (4x).
DC1 = 1, enables TACH measurements to be continuously made on TACH1. Fans must be driven
by dc. Setting this bit prevents pulse stretching because it is not required for dc−driven motors.
DC2 = 1, enables TACH measurements to be continuously made on TACH2. Fans must be driven
by dc. Setting this bit prevents pulse stretching because it is not required for dc−driven motors.
DC3 = 1, enables TACH measurements to be continuously made on TACH3. Fans must be driven
by dc. Setting this bit prevents pulse stretching because it is not required for dc−driven motors.
DC4 = 1, enables TACH measurements to be continuously made on TACH4. Fans must be driven
by dc. Setting this bit prevents pulse stretching because it is not required for dc−driven motors.
This bit is set high on the assertion of the THERM input and is cleared on read. If the THERM
assertion time exceeds 45.52 ms, this bit is set and becomes the LSB of the 8−bit TMR
reading. This allows THERM assertion times from 45.52 ms to 5.82 sec to be reported back
with a resolution of 22.76 ms.
Times how long THERM input is asserted. These seven bits read zero until the THERM
assertion time exceeds 45.52 ms.
Sets the maximum THERM assertion length allowed before an interrupt is generated. This
is an 8−bit limit with a resolution of 22.76 ms allowing THERM assertion limits of 45.52 ms
to 5.82 sec to be programmed. If the THERM assertion time exceeds this limit, Bit 5 (F4P)
of Interrupt Status Register 2 (0x42) is set. If the limit value is 0x00, an interrupt is generated
immediately on the assertion of the THERM input.
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Description
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