SW006012 Microchip Technology, SW006012 Datasheet - Page 114

• Manufacturer Part Number: SW006012
• Description: C COMPILER FOR DSPIC30F FAMILY
• Manufacturer: Microchip Technology
• Type: MPLAB® C30 Compilerr
• Series: PIC24 & DsPICr

Specifications of SW006012

• Supported Families: PIC24, DsPIC30F And DsPIC33F
• Core Architecture: PIC, DsPIC
• Kit Contents: Software And Docs
• Mcu Supported Families: PIC24 MCUs And DsPIC DSCs
• Tool Type: Compiler
• Processor Series: PIC24, dsPIC
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• For Use With/related Products: dsPIC30F
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MPLAB
DS51284F-page 108
®
C30 User’s Guide
EXAMPLE 7-4:
Finally, the compiler may choose to cache memory values in registers. These are often
referred to as register variables and are particularly prone to interrupt corruption, even
when an operation involving the variable is not being interrupted. Ensure that memory
resources shared between an ISR and an interruptible function are designated as
volatile. This will inform the compiler that the memory location may be updated
out-of-line from the serial code sequence. This will not protect against the effect of
non-atomic operations, but is never-the-less important.
7.9.2
Here are some strategies to remove potential hazards:
• Design the software system such that the conflicting event cannot occur. Do not
• Use care when sharing memory and, if possible, avoid sharing bit fields which
• Protect non-atomic updates of shared memory from interrupts as you would
7.9.3
The following example highlights some of the points discussed in this section:
void
int main(void) {
share memory between ISRs and other functions. Make ISRs as simple as
possible and move the real work to main code.
contain multiple bits.
protect critical sections of code. The following macro can be used for this purpose:
This macro disables interrupts by increasing the current priority level to 7,
performing the desired statement and then restoring the previous priority level.
/* More User Code */
LATGbits.LATG10 ^= 1;
LATG = 0x1238;
LATGbits.LATG5 = 1;
#define INTERRUPT_PROTECT(x) {
__
HigherPriorityInterrupt(void) {
/* User Code Here */
LATGbits.LATG15 = 1;
IPC0bits.INT0IP = 2;
}
attribute
char saved_ipl;
SET_AND_SAVE_CPU_IPL(saved_ipl,7);
x;
RESTORE_CPU_IPL(saved_ipl); } (void) 0;
Development Solutions
Application Example
__
CACHED MEMORY VALUES IN REGISTERS
((interrupt))
/* Potential HAZARD -
/* No problem, this is a write
/* No problem likely,
/* Set LATG bit 15 */
/* Set Interrupt 0
First reads LATG into a W reg,
implements XOR operation,
then writes result to LATG */
only assignment operation */
this is an assignment of a
single bit and will use a single
instruction bit set operation */
priority (multiple
bits involved) to 2 */
© 2007 Microchip Technology Inc.
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