DG-ACC-JBST Digi International, DG-ACC-JBST Datasheet - Page 18

• Manufacturer Part Number: DG-ACC-JBST
• Description: JTAG-BOOSTER FOR NETSILICON 3.3V
• Manufacturer: Digi International
• Series: Digi/FS Forthr
• Type: FLASHr

Specifications of DG-ACC-JBST

• Contents: Programmer and Associated Interface Software
• For Use With/related Products: NetSilicon NS9360, NS9750, NS9775
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: FS-9051; FS-9051

Reset Logic
Watchdog
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C o n n e c t C o r e X P 2 7 0 m o d u l e
The Connect Core XP 270 module has two reset signals:
Both signals are low-active. If RESET_IN# is activated outside the module (through
reset controller or reset button), the signal is first debounced by the on-board reset
circuitry (MAXIM MAX6390XS29D4 chip) and a reset signal is transmitted to the PXA270
processor. The reset input of the PXA270 can also be activated by a power-on
sequence.
Once the processor receives the reset input signal, it resets its internal peripherals
and a processor specific output reset signal — RESET_OUT# — becomes active. This
signal is available on ConnectCore XP 270 connectors.
On-board flash memories receive the reset signal through the RESET_IN# pin and the
Ethernet controller receives the reset signal through the RESET_OUT# signal.
Intel PXA270 power-on sequence timing is fully respected on the ConnectCore XP 270
module — no special care has to be taken outside the module. For more information
about power on timing, see “Intel PXA270 Processor Electrical, Mechanical and
Thermal Specification – Order Number 280002-004 p.64.”
The Intel XScale PXA270 processor comes with a watchdog unit. The processor’s
OSCR0 register can be programmed to generate a watchdog-reset signal. When the
OWER[WME] field is set, the OSCR0 register is compared to the OSMR3 register every
rising edge of the internal-made 3.25MHz clock.
If a match is detected, the OS timer asserts the internal WDOG_RST pin, which
asserts the RESET_OUT# pin. A reset is applied to the PXA270 processor and most
internal states are cleared.
Once enabled, the watchdog function can be disabled only by one of the reset
functions (hardware reset, watchdog reset, or GPIO reset). Writing a zero to the
Watchdog Match Enable bit after it has been set has no effect.
For more information about the watchdog unit, see the “Intel PXA27x Processor
Family Developer’s Manual – Order Number: 280000-002”.
RESET_IN#
RESET_OUT#
C o n n e c t C o r e X P 2 7 0 H a r d w a r e R e f e r e n c e , R e v . B
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