PESD5V0U4BW,115 NXP Semiconductors, PESD5V0U4BW,115 Datasheet - Page 7

• Manufacturer Part Number: PESD5V0U4BW,115
• Description: DIODE ARRAY ESD BI-DIR SOT-665
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of PESD5V0U4BW,115

• Package / Case: SOT-665
• Voltage - Reverse Standoff (typ): 5V
• Voltage - Breakdown: 5.5V
• Polarization: 4 Channel Array - Bidirectional
• Mounting Type: Surface Mount
• Polarity: Bidirectional
• Channels: 4 Channels
• Operating Voltage: 5 V
• Breakdown Voltage: 6.5 V
• Capacitance: 2.9 pF
• Maximum Operating Temperature: + 150 C
• Minimum Operating Temperature: - 55 C
• Dimensions: 1.3 mm W x 1.7 mm L x 0.6 mm H
• Mounting Style: SMD/SMT
• Power (watts): -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 934061953115

NXP Semiconductors
7. Application information
8. Test information
PESD5V0U4BF_PESD5V0U4BW_1
Product data sheet
8.1 Quality information
The PESD5V0U4BF and the PESD5V0U4BW are designed for the protection of up to four
bidirectional data or signal lines from the damage caused by ESD and surge pulses. The
devices may be used on lines where the signal polarities are both, positive and negative
with respect to ground.
Circuit board layout and protection device placement
Circuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT)
and surge transients. The following guidelines are recommended:
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q101 - Stress test qualification for discrete semiconductors , and is
suitable for use in automotive applications.
1. Place the device as close to the input terminal or connector as possible.
2. The path length between the device and the protected line should be minimized.
3. Keep parallel signal paths to a minimum.
4. Avoid running protected conductors in parallel with unprotected conductors.
5. Minimize all Printed-Circuit Board (PCB) conductive loops including power and
6. Minimize the length of the transient return path to ground.
7. Avoid using shared transient return paths to a common ground point.
8. Ground planes should be used whenever possible. For multilayer PCBs, use ground
Fig 5.
ground loops.
vias.
Application diagram
Ultra low capacitance bidirectional quadruple ESD protection arrays
PESD5V0U4BF; PESD5V0U4BW
Rev. 01 — 15 August 2008
1
2
3
DUT
data- or transmission lines
6
5
4
006aab335
© NXP B.V. 2008. All rights reserved.
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