PIC16F887-I/ML Microchip Technology, PIC16F887-I/ML Datasheet - Page 205

• Manufacturer Part Number: PIC16F887-I/ML
• Description: IC PIC MCU FLASH 8KX14 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F887-I/ML

• Program Memory Type: FLASH
• Program Memory Size: 14KB (8K x 14)
• Package / Case: 44-QFN
• Mfg Application Notes: Intro to Capacitive Sensing Appl Notes Layout and Physical Design Appl Note
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: MSSP/EUSART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 53273-916
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM164123, DM164120-3, DV164122
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN444-1001 - DEMO BOARD FOR PICMICRO MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

13.4.15
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset, or when the
MSSP module is disabled. Control of the I
be taken when the P bit (SSPSTAT register) is set, or
the bus is idle with both the S and P bits clear. When
the bus is busy, enabling the SSP Interrupt will gener-
ate the interrupt when the Stop condition occurs.
In Multi-Master operation, the SDA line must be moni-
tored for arbitration, to see if the signal level is the
expected output level. This check is performed in hard-
ware, with the result placed in the BCLIF bit.
Arbitration can be lost in the following states:
• Address transfer
• Data transfer
• A Start condition
• A Repeated Start condition
• An Acknowledge condition
13.4.16
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ‘1’ on SDA, by letting SDA float high and
another master asserts a ‘0’. When the SCL pin floats
high, data should be stable. If the expected data on
FIGURE 13-20:
© 2009 Microchip Technology Inc.
SDA
SCL
BCLIF
MULTI-MASTER MODE
MULTI -MASTER
COMMUNICATION, BUS
COLLISION, AND BUS
ARBITRATION
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Data changes
while SCL = 0
2
C bus may
SDA released
PIC16F882/883/884/886/887
by master
SDA line pulled low
by another source
SDA is a ‘1’ and the data sampled on the SDA pin = 0,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag (BCLIF) and reset the
I
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF bit is
cleared, the SDA and SCL lines are de-asserted, and
the SSPBUF can be written to. When the user services
the bus collision interrupt service routine, and if the I
bus is free, the user can resume communication by
asserting a Start condition.
If a Start, Repeated Start, Stop, or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are de-asserted, and the respective control bits in
the SSPCON2 register are cleared. When the user
services the bus collision interrupt service routine, and
if the I
communication by asserting a Start condition.
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPIF bit will be
set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the trans-
mitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the
determination of when the bus is free. Control of the I
bus can be taken when the P bit is set in the SSPSTAT
register, or the bus is idle and the S and P bits are
cleared.
2
C port to its Idle state (Figure 13-20).
2
C bus is free, the user can resume
Sample SDA,
While SCL is high, data doesn’t
match what is driven by the master,
Bus collision has occurred
Set bus collision
interrupt (BCLIF)
DS41291F-page 203
2
2
C
C