PIC18F25J11-I/ML Microchip Technology, PIC18F25J11-I/ML Datasheet - Page 365

• Manufacturer Part Number: PIC18F25J11-I/ML
• Description: IC PIC MCU FLASH 32K 2V 28-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F25J11-I/ML

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC18
• No. Of I/o's: 16
• Ram Memory Size: 3.6875KB
• Cpu Speed: 48MHz
• No. Of Timers: 5
• Interface: EUSART, I2C, SPI
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3776 B
• Interface Type: EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136, MA180023
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

22.2
The full range of voltage reference cannot be realized
due to the construction of the module. The transistors
on the top and bottom of the resistor ladder network
(see Figure 22-1) keep CV
reference source rails. The voltage reference is derived
from the reference source; therefore, the CV
changes with fluctuations in that source. The tested
absolute accuracy of the voltage reference can be
found in Section 28.0 “Electrical Characteristics”.
22.3
The voltage reference module operates independently
of the comparator module. The output of the reference
generator may be connected to the RA2 pin if the
CVROE bit is set. Enabling the voltage reference out-
put onto RA2 when it is configured as a digital input will
increase current consumption. Connecting RA2 as a
digital output with CVRSS enabled will also increase
current consumption.
FIGURE 22-2:
TABLE 22-1:
© 2009 Microchip Technology Inc.
CVRCON
CM1CON
CM2CON
TRISA
ANCON0
ANCON1
Legend: — = unimplemented, read as ‘0’, r = reserved. Shaded cells are not used with the comparator voltage
Note 1:
Name
Note 1:
Voltage Reference Accuracy/Error
Connection Considerations
reference.
These bits are only available on 44-pin devices.
PCFG7
R is dependent upon the Comparator Voltage Reference Configuration bits, CVRCON<5> and CVRCON<3:0>.
CVREN
TRISA7
VBGEN
CON
CON
Bit 7
REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
CV
Module
COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
(1)
PIC18F46J11
REF
PCFG6
REF
CVROE
TRISA6
COE
COE
Bit 6
Impedance
Reference
r
Voltage
from approaching the
Output
R
(1)
(1)
PCFG5
TRISA5
CVRR
CPOL
CPOL
Bit 5
—
RA2
REF
(1)
output
EVPOL1
EVPOL1
PCFG12
CVRSS
PCFG4
Bit 4
—
EVPOL0
EVPOL0
PCFG11
PIC18F46J11 FAMILY
TRISA3
PCFG3
CVR3
The RA2 pin can be used as a simple D/A output with
limited drive capability. Due to the limited current drive
capability, a buffer must be used on the voltage
reference output for external connections to V
Figure 22-2 for an example buffering technique.
22.4
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the CVRCON register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
22.5
A device Reset disables the voltage reference by
clearing bit, CVREN (CVRCON<7>). This Reset also
disconnects the reference from the RA2 pin by clearing
bit, CVROE (CVRCON<6>) and selects the high-voltage
range by clearing bit, CVRR (CVRCON<5>). The CVR
value select bits are also cleared.
Bit 3
Operation During Sleep
Effects of a Reset
+
–
PCFG10
TRISA2
PCFG2
CVR2
CREF
CREF
Bit 2
TRISA1
PCFG1
PCFG9
CVR1
CCH1
CCH1
CV
Bit 1
REF
Output
TRISA0
PCFG0
PCFG8
CCH0
CCH0
CVR0
Bit 0
DS39932C-page 365
on Page:
Values
REF
Reset
68
64
64
66
68
68
. See