PIC18F25J11-I/ML Microchip Technology, PIC18F25J11-I/ML Datasheet - Page 84

• Manufacturer Part Number: PIC18F25J11-I/ML
• Description: IC PIC MCU FLASH 32K 2V 28-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F25J11-I/ML

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC18
• No. Of I/o's: 16
• Ram Memory Size: 3.6875KB
• Cpu Speed: 48MHz
• No. Of Timers: 5
• Interface: EUSART, I2C, SPI
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3776 B
• Interface Type: EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136, MA180023
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F46J11 FAMILY
TABLE 5-4:
DS39932C-page 84
FSR1H
FSR1L
BSR
INDF2
POSTINC2
POSTDEC2
PREINC2
PLUSW2
FSR2H
FSR2L
STATUS
TMR0H
TMR0L
T0CON
OSCCON
CM1CON
CM2CON
RCON
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSP1BUF
SSP1ADD
SSP1MSK
SSP1STAT
SSP1CON1
SSP1CON2
ADRESH
ADRESL
ADCON0
ADCON1
WDTCON
PSTR1CON
ECCP1AS
ECCP1DEL
CCPR1H
CCPR1L
CCP1CON
Legend:
Note
File Name
1:
2:
3:
4:
5:
6:
(4)
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs.
Bit 21 of the PC is only available in Serial Programming (SP) modes.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
Alternate names and definitions for these bits when the MSSP module is operating in I
Masking Modes” for details.
These bits and/or registers are only available in 44-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 44-pin devices.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have
different functions determined by the module’s operating mode. See Section 10.1.2 “Data Registers” for more information.
Indirect Data Memory Address Pointer 1 Low Byte
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
Indirect Data Memory Address Pointer 2 Low Byte
Timer0 Register High Byte
Timer0 Register Low Byte
Timer1 Register High Byte
Timer1 Register Low Byte
Timer2 Register
Timer2 Period Register
MSSP1 Receive Buffer/Transmit Register
MSSP1 Address Register (I
A/D Result Register High Byte
A/D Result Register Low Byte
Capture/Compare/PWM Register 1 HIgh Byte
Capture/Compare/PWM Register 1 Low Byte
ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0
TMR1CS1
TMR0ON
REGSLP
P1RSEN
VCFG1
CMPL1
IDLEN
WCOL
GCEN
GCEN
MSK7
ADFM
P1M1
Bit 7
CON
CON
IPEN
SMP
—
—
—
—
—
REGISTER FILE SUMMARY (PIC18F46J11 FAMILY) (CONTINUED)
T2OUTPS3 T2OUTPS2 T2OUTPS1
TMR1CS0
ACKSTAT
ACKSTAT
LVDSTAT
SSPOV
VCFG0
ADCAL
T08BIT
CMPL0
P1DC6
IRCF2
MSK6
P1M0
Bit 6
COE
COE
CKE
—
—
—
—
—
ADMSK5
2
T1CKPS1
C™ Slave mode), MSSP1 Baud Rate Reload Register (I
ULPLVL
ACKDT
SSPEN
ACQT2
P1DC5
DC1B1
IRCF1
CPOL
CPOL
MSK5
T0CS
CHS3
Bit 5
D/A
CM
—
—
—
—
—
(4)
ADMSK4
STRSYNC
T1CKPS0
EVPOL1
EVPOL1
ACKEN
ACQT1
P1DC4
DC1B0
IRCF0
MSK4
T0SE
CHS2
Bit 4
CKP
—
—
—
RI
—
N
P
(4)
Indirect Data Memory Address Pointer 1 High Byte
Bank Select Register
Indirect Data Memory Address Pointer 2 High Byte
T2OUTPS0
ADMSK3
T1OSCEN
PSS1AC1
CCP1M3
EVPOL0
EVPOL0
OSTS
SSPM3
ACQT0
P1DC3
MSK3
RCEN
CHS1
STRD
Bit 3
PSA
OV
TO
DS
S
(2)
(4)
ADMSK2
PSS1AC0
TMR2ON
T1SYNC
CCP1M2
SSPM2
ADCS2
ULPEN
P1DC2
T0PS2
CREF
CREF
MSK2
CHS0
STRC
Bit 2
PEN
R/W
PD
—
Z
(4)
2
C™ Slave mode. See Section 18.5.3.2 “Address
2
ADMSK1
GO/DONE
PSS1BD1
T2CKPS1
C Master mode)
ULPSINK
CCP1M1
SSPM1
ADCS1
P1DC1
T0PS1
SCS1
CCH1
CCH1
MSK1
RSEN
STRB
RD16
Bit 1
POR
DC
UA
© 2009 Microchip Technology Inc.
(4)
T2CKPS0 -000 0000 64, 207
PSS1BD0 0000 0000
TMR1ON
SWDTEN 1xx- 0000 64, 400
CCP1M0
SSPM0
ADCS0
P1DC0
T0PS0
ADON
SCS0
CCH0
CCH0
MSK0
STRA
Bit 0
BOR
SEN
SEN
BF
C
---- xxxx 63, 91
xxxx xxxx 63, 91
---- 0000 63, 78
---- xxxx 64, 91
xxxx xxxx 64, 91
---x xxxx 64, 89
0000 0000
xxxx xxxx
1111 1111 64, 191
0110 q-00 64, 38
0001 1111 64, 356
0001 1111 64, 356
0-11 1100 64, 123
xxxx xxxx
xxxx xxxx
0000 0000 64, 195
0000 0000
1111 1111
xxxx xxxx
0000 0000
1111 1111 64, 289
0000 0000 64, 286
0000 0000 64, 287
0000 0000 64, 288
xxxx xxxx
xxxx xxxx
0000 0000 64, 345
0000 0000 64, 346
00-0 0001 64, 261
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
POR, BOR
Value on
N/A
N/A
N/A
N/A
N/A
Details
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