PIC24FJ48GA002-I/SS Microchip Technology, PIC24FJ48GA002-I/SS Datasheet - Page 153

• Manufacturer Part Number: PIC24FJ48GA002-I/SS
• Description: IC PIC MCU FLASH 48K 28-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ48GA002-I/SS

• Core Size: 16-Bit
• Program Memory Size: 48KB (16K x 24)
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Controller Family/series: PIC24
• No. Of I/o's: 21
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• No. Of Pwm Channels: 5
• Embedded Interface Type: I2C, SPI, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164338 - MOD SKT PIC24F/DSPIC33F 28SOICDV164033 - KIT START EXPLORER 16 MPLAB ICD2
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

16.3
To compute the Baud Rate Generator reload value, use
Equation 16-1.
EQUATION 16-1:
TABLE 16-1:
TABLE 16-2:
 2010 Microchip Technology Inc.
Note 1:
Note 1:
0000 000
0000 000
0000 001
0000 010
0000 011
0000 1xx
1111 1xx
1111 0xx
Note 1: Based on F
Address
Slave
2:
3:
Required
100 kHz
100 kHz
100 kHz
400 kHz
400 kHz
400 kHz
400 kHz
System
Setting Baud Rate When
Operating as a Bus Master
1 MHz
1 MHz
1 MHz
F
I2CxBRG
F
The address bits listed here will never cause an address match, independent of the address mask settings.
Address will be Acknowledged only if GCEN = 1.
Match on this address can only occur on the upper byte in 10-Bit Addressing mode.
SCL
or
Based on F
SCL
PLL are disabled.
=
R/W
Bit
I
I
0
1
x
x
x
x
x
x
2
2
--------------------------------------------------------------------- -
I2CxBRG
C™ CLOCK RATES
C™ RESERVED ADDRESSES
=
COMPUTING BAUD RATE
RELOAD VALUE


CY
CY
----------- -
F
General Call Address
Start Byte
Cbus Address
Reserved
Reserved
HS Mode Master Code
Reserved
10-Bit Slave Upper Byte
F
SCL
CY
= F
= F
+ +
–
OSC
F
OSC
1
----------------------------- -
10 000 000
CY
16 MHz
16 MHz
16 MHz

8 MHz
4 MHz
8 MHz
4 MHz
2 MHz
8 MHz
4 MHz
/2, Doze mode and PLL are disabled.
----------------------------- -
10 000 000
/2; Doze mode and
F
F
CY
CY


F
CY

(1)


(1)
–
1
(2)
(3)
PIC24FJ64GA004 FAMILY
(Decimal)
(1)
157
78
39
37
18
13
9
4
6
3
I2CxBRG Value
16.4
The I2CxMSK register (Register 16-3) designates
address bit positions as “don’t care” for both 7-Bit and
10-Bit Addressing modes. Setting a particular bit loca-
tion (= 1) in the I2CxMSK register causes the slave
module to respond whether the corresponding address
bit value is a ‘0’ or a ‘1’. For example, when I2CxMSK
is set to ‘00100000’, the slave module will detect both
addresses, ‘0000000’ and ‘00100000’.
To enable address masking, the IPMI (Intelligent
Peripheral Management Interface) must be disabled by
clearing the IPMIEN bit (I2CxCON<11>).
Description
Note:
(Hexadecimal)
Slave Address Masking
As a result of changes in the I
col, the addresses in Table 16-2 are
reserved and will not be Acknowledged in
Slave mode. This includes any address
mask settings that include any of these
addresses.
9D
4E
27
25
12
D
9
4
6
3
1.026 MHz
1.026 MHz
0.909 MHz
DS39881D-page 153
100 kHz
100 kHz
404 kHz
404 kHz
385 kHz
385 kHz
Actual
99 kHz
F
SCL
2
C™ proto-