PIC24FJ48GA002-I/SS Microchip Technology, PIC24FJ48GA002-I/SS Datasheet - Page 215

IC PIC MCU FLASH 48K 28-SSOP

PIC24FJ48GA002-I/SS

Manufacturer Part Number
PIC24FJ48GA002-I/SS
Description
IC PIC MCU FLASH 48K 28-SSOP
Manufacturer
Microchip Technology
Series
PIC® 24Fr

Specifications of PIC24FJ48GA002-I/SS

Core Size
16-Bit
Program Memory Size
48KB (16K x 24)
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Controller Family/series
PIC24
No. Of I/o's
21
Ram Memory Size
8KB
Cpu Speed
32MHz
No. Of Timers
5
No. Of Pwm Channels
5
Embedded Interface Type
I2C, SPI, UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164338 - MOD SKT PIC24F/DSPIC33F 28SOICDV164033 - KIT START EXPLORER 16 MPLAB ICD2
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC24FJ48GA002-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
24.3.1
The Watchdog Timer has an optional Fixed Window
mode of operation. In this Windowed mode, CLRWDT
instructions can only reset the WDT during the last 1/4
of the programmed WDT period. A CLRWDT instruction
executed before that window causes a WDT Reset,
similar to a WDT time-out.
Windowed WDT mode is enabled by programming the
WINDIS Configuration bit (CW1<6>) to ‘0’.
FIGURE 24-2:
24.4
PIC24FJ64GA004 family devices implement a JTAG
interface, which supports boundary scan device
testing.
24.5
For all devices in the PIC24FJ64GA004 family of
devices, the on-chip program memory space is treated
as a single block. Code protection for this block is
controlled by one Configuration bit, GCP. This bit
inhibits external reads and writes to the program
memory space. It has no direct effect in normal
execution mode.
Write protection is controlled by the GWRP bit in the
Configuration Word. When GWRP is programmed to
‘0’, internal write and erase operations to program
memory are blocked.
 2010 Microchip Technology Inc.
Sleep or Idle Mode
New Clock Source
All Device Resets
CLRWDT Instr.
PWRSAV Instr.
Exit Sleep or
Transition to
LPRC Input
JTAG Interface
Program Verification and
Code Protection
Idle Mode
SWDTEN
FWDTEN
WINDOWED OPERATION
WDT BLOCK DIAGRAM
31 kHz
(5-bit/7-bit)
Prescaler
FWPSA
1 ms/4 ms
LPRC Control
PIC24FJ64GA004 FAMILY
Counter
WDT
24.3.2
The WDT is enabled or disabled by the FWDTEN
Configuration bit. When the FWDTEN Configuration bit
is set, the WDT is always enabled.
The WDT can be optionally controlled in software when
the FWDTEN Configuration bit has been programmed
to ‘0’. The WDT is enabled in software by setting the
SWDTEN control bit (RCON<5>). The SWDTEN
control bit is cleared on any device Reset. The software
WDT option allows the user to enable the WDT for
critical code segments and disable the WDT during
non-critical segments for maximum power savings.
24.5.1
The Configuration registers are protected against
inadvertent or unwanted changes or reads in two ways.
The primary protection method is the same as that of
the RP registers – shadow registers contain a compli-
mentary value which is constantly compared with the
actual value.
To safeguard against unpredictable events, Configura-
tion bit changes resulting from individual cell level
disruptions (such as ESD events) will cause a parity
error and trigger a device Reset.
The data for the Configuration registers is derived from
the Flash Configuration Words in program memory.
When the GCP bit is set, the source data for device
configuration is also protected as a consequence.
WDTPS3:WDTPS0
1:1 to 1:32.768
Postscaler
CONTROL REGISTER
CONFIGURATION REGISTER
PROTECTION
DS39881D-page 215
WDT Overflow
Wake from Sleep
Reset

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