PIC18F4431-I/PT Microchip Technology, PIC18F4431-I/PT Datasheet - Page 180

IC PIC MCU FLASH 8KX16 44TQFP

PIC18F4431-I/PT

Manufacturer Part Number
PIC18F4431-I/PT
Description
IC PIC MCU FLASH 8KX16 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F4431-I/PT

Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
44-TQFP, 44-VQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
Number Of I /o
36
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
EUSART/I2C/SPI/SSP
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
36
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Package
44TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F4431-I/PT
Manufacturer:
MICROCHIP
Quantity:
1 400
Part Number:
PIC18F4431-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F4431-I/PT
Manufacturer:
MICROCHI
Quantity:
20 000
PIC18F2331/2431/4331/4431
16.3
The Motion Feedback module includes three noise
rejection filters on CAP1/INDX, CAP2/QEA and
CAP3/QEB. The filter block also includes a fourth filter
for the T5CKI pin. They are intended to help reduce
spurious noise spikes which may cause the input sig-
nals to become corrupted at the inputs. The filter
ensures that the input signals are not permitted to
change until a stable value has been registered for
three consecutive sampling clock cycles.
The filters are controlled using the Digital Filter Control
(DFLTCON) register (see Register 16-3). The filters
can be individually enabled or disabled by setting or
clearing the corresponding FLTxEN bit in the
DFLTCON register. The sampling frequency, which
must be the same for all three noise filters, can be
REGISTER 16-3:
DS39616B-page 178
Noise Filters
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
Unimplemented: Read as ‘0’
FLT4EN: Noise Filter Output Enable bit, T5CKI input
1 = Enabled
0 = Disabled
FLT3EN: Noise Filter Output Enable bit, CAP3/QEB input
1 = Enabled
0 = Disabled
FLT2EN: Noise Filter Output Enable bit, CAP2/QEA input
1 = Enabled
0 = Disabled
FLT1EN: Noise Filter Output Enable bit, CAP1/INDX input
1 = Enabled
0 = Disabled
FLTCK<2:0>: Noise Filter Clock Divider Ratio bits
111 =Unused
110 =1:128
101 =1:64
100 =1:32
011 =1:16
010 =1:4
001 =1:2
000 =1:1
bit 7
Legend:
R = Readable bit
-n = Value at POR
DFLTCON: DIGITAL FILTER CONTROL REGISTER
Note:
Note 1: Noise Filter Output Enables are functional in both QEI and IC operating modes
U-0
The Noise Filter is intended for random high-frequency filtering and not continuous
high-frequency filtering.
FLT4EN
R/W-0
FLT3EN
R/W-0
Preliminary
W = Writable bit
‘1’ = bit is set
FLT2EN
R/W-0
programmed by the FLTCK2:FLTCK0 configuration
bits. T
divider block.
The noise filters can either be added or removed from
the input capture or QEI signal path by setting or
clearing the appropriate FLTxEN bit, respectively. Each
capture channel provides for individual enable control
of the filter output. The FLT4EN bit enables or disabled
the noise filter available on TMR5CKI input in the
Timer5 module.
The filter network for all channels is disabled on POR
and BOR resets , as the DFLTCON register is cleared
on resets. The operation of the filter is shown in the
timing diagram in Figure 16-14.
CY
U = Unimplemented bit, read as ‘0’
‘0’ = bit is cleared
is used as the clock reference to the clock
FLT1EN
R/W-0
(1)
(1)
(1)
FLTCK2
R/W-0
 2003 Microchip Technology Inc.
x = bit is unknown
FLTCK1
R/W-0
FLTCK0
R/W-0
bit 0

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