PIC18F4431-I/PT Microchip Technology, PIC18F4431-I/PT Datasheet - Page 35

• Manufacturer Part Number: PIC18F4431-I/PT
• Description: IC PIC MCU FLASH 8KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART/I2C/SPI/SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9-ch x 10-bit
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 3-2:
3.2
The power-managed Sleep mode in the PIC18F2331/
2431/4331/4431 devices is identical to that offered in
all other PICmicro
the IDLEN and SCS1:SCS0 bits (this is the Reset
state), and executing the SLEEP instruction. This shuts
down the primary oscillator and the OSTS bit is cleared
(see Figure 3-1).
When a wake event occurs in Sleep mode (by interrupt,
Reset, or WDT time-out), the system will not be clocked
until the primary clock source becomes ready (see
Figure 3-2), or it will be clocked from the internal oscil-
lator block if either the Two-Speed Start-up or the Fail-
Safe Clock Monitor are enabled (see Section 22.0
“Special Features of the CPU”). In either case, the
OSTS bit is set when the primary clock provides the
system clocks. The IDLEN and SCS bits are not
affected by the wake-up.
 2003 Microchip Technology Inc.
Sleep
Any idle mode
Any run mode
Managed
Power
Mode
Sleep Mode
®
COMPARISON BETWEEN POWER-MANAGED MODES
Not clocked (not running) Wake-up
Not clocked (not running) Wake-up
Secondary, or INTOSC
multiplexer
controllers. It is entered by clearing
CPU is clocked by ...
PIC18F2331/2431/4331/4431
Reset
WDT time-out
causes a ...
Preliminary
Not clocked
Primary, Secondary or
INTOSC multiplexer
Secondary or INTOSC
multiplexer
3.3
The IDLEN bit allows the controller’s CPU to be selec-
tively shut down while the peripherals continue to oper-
ate. Clearing IDLEN allows the CPU to be clocked.
Setting IDLEN disables clocks to the CPU, effectively
stopping program execution (see Register 2-2). The
peripherals continue to be clocked regardless of the
setting of the IDLEN bit.
There is one exception to how the IDLEN bit functions.
When all the low-power OSCCON bits are cleared
(IDLEN:SCS1:SCS0 = 000), the device enters Sleep
mode upon the execution of the SLEEP instruction. This
is both the Reset state of the OSCCON register and the
setting that selects Sleep mode. This maintains com-
patibility with other PICmicro devices that do not offer
power-managed modes.
If the Idle Enable bit, IDLEN (OSCCON<7>), is set to a
‘1’ when a SLEEP instruction is executed, the
peripherals will be clocked from the clock source
selected using the SCS1:SCS0 bits; however, the CPU
will not be clocked. Since the CPU is not executing
instructions, the only exits from any of the idle modes
are by interrupt, WDT time-out or a Reset.
When a wake event occurs, CPU execution is delayed
approximately 10 µs while it becomes ready to execute
code. When the CPU begins executing code, it is
clocked by the same clock source as was selected in
the power-managed mode (i.e., when waking from
RC_IDLE mode, the internal oscillator block will clock
the CPU and peripherals until the primary clock source
becomes ready – this is essentially RC_RUN mode).
This continues until the primary clock source becomes
ready. When the primary clock becomes ready, the
OSTS bit is set, and the system clock source is
switched to the primary clock (see Figure 3-4). The
IDLEN and SCS bits are not affected by the wake-up.
While in any idle mode or the Sleep mode, a WDT time-
out will result in a WDT wake-up to full power operation.
Peripherals are
clocked by ...
Idle Modes
None or INTOSC multiplexer
if Two-Speed Start-up or
Fail-Safe Clock Monitor are
enabled.
Unchanged from Idle mode
(CPU operates as in
corresponding Run mode).
Unchanged from Run mode.
(while primary becomes
Clock during wake-up
ready)
DS39616B-page 33