PIC18F4431-I/PT Microchip Technology, PIC18F4431-I/PT Datasheet - Page 391

• Manufacturer Part Number: PIC18F4431-I/PT
• Description: IC PIC MCU FLASH 8KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART/I2C/SPI/SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9-ch x 10-bit
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Timing Diagrams and Specifications ................................ 355
 2003 Microchip Technology Inc.
Example SPI Master Mode (CKE = 0) ..................... 361
Example SPI Master Mode (CKE = 1) ..................... 362
Example SPI Slave Mode (CKE = 0) ....................... 363
Example SPI Slave Mode (CKE = 1) ....................... 364
External Clock (All Modes except PLL) .................... 355
Fail-Safe Clock Monitor ............................................ 282
I
I
I
I
Low-Voltage Detect .................................................. 264
Low-Voltage Detect Characteristics ......................... 352
Master SSP I
Master SSP I
PWM Output ............................................................ 156
Reset, Watchdog Timer (WDT), Oscillator Start-up
Send Break Character Sequence ............................ 236
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ......................................... 215
SPI Mode (Slave Mode with CKE = 0) ..................... 215
SPI Mode (Slave Mode with CKE = 1) ..................... 216
Synchronous Reception (Master Mode, SREN) ...... 239
Synchronous Transmission ...................................... 237
Synchronous Transmission (Through TXEN) .......... 238
Time-out Sequence on POR w/PLL Enabled
Time-out Sequence on Power-up (MCLR Not
Time-out Sequence on Power-up (MCLR Not
Time-out Sequence on Power-up (MCLR
Timer0 and Timer1 External Clock .......................... 359
Transition for Entry to SEC_IDLE Mode .................... 36
Transition for Entry to SEC_RUN Mode .................... 38
Transition for Entry to Sleep Mode ............................ 34
Transition for Two-Speed Start-up
Transition for Wake from RC_RUN Mode
Transition for Wake from SEC_RUN Mode
Transition for Wake from Sleep (HSPLL) ................... 34
Transition Timing For Wake From PRI_IDLE Mode ... 35
Transition Timing to PRI_IDLE Mode ........................ 35
Transition to RC_IDLE Mode ..................................... 37
Transition to RC_RUN Mode ..................................... 39
USART Synchronous Receive ( Master/Slave) ........ 369
USART SynchronousTransmission
Capture/Compare/PWM Requirements ................... 360
CLKO and I/O Requirements ................................... 357
DC Characteristics - Internal RC Accuracy .............. 356
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Slave Mode Requirements
External Clock Requirements .................................. 355
2
2
2
2
C Bus Data ............................................................ 365
C Bus Start/Stop Bits ............................................. 365
C Reception (7-bit Address) .................................. 219
C Transmission (7-bit Address) ............................. 219
Timer (OST), Power-up Timer (PWRT) ........... 358
V
(MCLR Tied to V
Tied to V
Tied to V
Tied to V
(INTOSC to HSPLL) ......................................... 280
(RC_RUN to NFP) ............................................. 37
(Secondary Clock to HSPLL) ............................. 36
(Master/Slave) .................................................. 369
(Master Mode, CKE = 0) .................................. 361
(Master Mode, CKE = 1) .................................. 362
(Slave Mode, CKE = 0) .................................... 363
(CKE = 1) ......................................................... 364
DD
Rise > T
2
2
DD
DD
DD
C Bus Data ........................................ 367
C Bus Start/Stop Bits ........................ 367
): Case 1 .......................................... 54
): Case 2 .......................................... 54
, V
PWRT
DD
DD
Rise < T
) ............................................ 55
) ........................................... 55
PWRT
DD
,
) ........................ 54
PIC18F2331/2431/4331/4431
Top-of-Stack Access .......................................................... 58
TSTFSZ ........................................................................... 328
Two-Speed Start-up ..................................................267, 279
Two-Word Instructions
TXSTA Register
U
UA .................................................................................... 212
Update Address bit, UA ................................................... 212
USART
W
Watchdog Timer (WDT) ............................................267, 278
WCOL bit ......................................................................... 213
Write Collision Detect bit (WCOL) ................................... 213
WWW, On-Line Support ...................................................... 6
X
XORLW ............................................................................ 328
XORWF ........................................................................... 329
I
Master SSP I
Master SSP I
PLL Clock ................................................................ 356
RESET, Watchdog Timer, Oscillator Start-up
Timer0 and Timer1 External Clock Requirements ... 359
USART Synchronous Receive Requirements ......... 369
USART Synchronous Transmission
Example Cases .......................................................... 62
BRGH Bit ................................................................. 225
Asynchronous Mode ................................................ 230
Baud Rate Generator (BRG) ................................... 225
Serial Port Enable (SPEN Bit) ................................. 221
Synchronous Master Mode ...................................... 237
Synchronous Slave Mode ........................................ 241
Associated Registers ............................................... 279
Control Register ....................................................... 278
During Oscillator Failure .......................................... 281
Programming Considerations .................................. 278
2
C Bus Data Requirements (Slave Mode) .............. 366
Requirements .................................................. 367
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 358
Requirements .................................................. 369
12-bit Break Transmit and Receive ................. 236
Associated Registers, Receive ........................ 234
Associated Registers, Transmit ....................... 232
Auto-Wake-up on Sync Break ......................... 235
Receiver .......................................................... 233
Setting up 9-bit Mode with Address Detect ..... 233
Transmitter ...................................................... 230
Associated Registers ....................................... 226
Auto-Baud Rate Detect .................................... 229
Baud Rate Error, Calculating ........................... 225
Baud Rates, Asynchronous Modes ................. 226
High Baud Rate Select (BRGH Bit) ................. 225
Power-Managed Mode Operation ................... 225
Sampling .......................................................... 225
Associated Registers, Reception ..................... 240
Associated Registers, Transmit ....................... 238
Reception ........................................................ 239
Transmission ................................................... 237
Associated Registers, Receive ........................ 242
Associated Registers, Transmit ....................... 241
Reception ........................................................ 242
Transmission ................................................... 241
2
2
C Bus Data Requirements ................ 368
C Bus Start/Stop Bits
DS39616B-page 389