P87C591VFA/00,512 NXP Semiconductors, P87C591VFA/00,512 Datasheet - Page 22

IC 80C51 MCU 16K OTP 44-PLCC

P87C591VFA/00,512

Manufacturer Part Number
P87C591VFA/00,512
Description
IC 80C51 MCU 16K OTP 44-PLCC
Manufacturer
NXP Semiconductors
Series
87Cr
Datasheet

Specifications of P87C591VFA/00,512

Core Processor
8051
Core Size
8-Bit
Speed
12MHz
Connectivity
CAN, EBI/EMI, I²C, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (16K x 8)
Program Memory Type
OTP
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.75 V ~ 5.25 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Processor Series
P87C5x
Core
80C51
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
CAN, I2C, UART
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
568-1256-5
935268182512
P87C591VFAA

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
P87C591VFA/00,512
Manufacturer:
TI
Quantity:
8
Part Number:
P87C591VFA/00,512
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
11 LOW POWER MODES
11.1
The static design enables the clock speed to be reduced
down to 0 MHz (stopped). When the oscillator is stopped,
the RAM and Special Function Registers retain their
values. This mode allows step-by-step utilization and
permits reduced system power consumption by lowering
the clock frequency down to any value. For lowest power
consumption the Power-down mode is suggested.
11.2
In the Idle mode (see Table 7), the CPU puts itself to sleep
while all of the on-chip peripherals stay active. The
instruction to invoke the idle mode is the last instruction
executed in the normal operating mode before the Idle
mode is activated. The CPU contents, the on-chip RAM,
and all of the special function registers remain intact during
this mode. The Idle mode can be terminated either by any
enabled interrupt (at which time the process is picked up
at the interrupt service routine and continued), or by a
hardware reset which starts the processor in the same
manner as a Power-on reset.
Table 7
With an external interrupt, INT0 and INT1 must be enabled and configured as level-sensitive. Holding the pin low restarts
the oscillator but bringing the pin back high completes the exit. Once the interrupt is serviced, the next instruction to be
executed after RETI will be the one following the instruction that put the device into Power-down.
2000 Jul 26
Idle
Power-down
Single-chip 8-bit microcontroller with CAN controller
MODE
Stop Clock Mode
Idle Mode
Status of external pins during Idle and Power-down modes
internal
external
internal
external
MEMORY
ALE
1
1
0
0
PSEN
1
1
0
0
port data
float
port data
float
PORT 0
22
11.3
To save even more power, a Power-down mode (see
Table 7) can be invoked by software. In this mode, the
oscillator is stopped and the instruction that invoked Power
Down is the last instruction executed. The on-chip RAM
and Special Function Registers retain their values down to
2.0 V and care must be taken to return V
specified operating voltages before the Power-down Mode
is terminated.
A hardware reset or external interrupt can be used to exit
from Power-down. The Wake-up from Power-down bit,
WUPD (AUXR1.3) must be set in order for an interrupt to
cause a Wake-up from Power-down. Reset redefines all
the SFRs but does not change the on-chip RAM. A
Wake-up allows both the SFRs and the on-chip RAM to
retain their values.
To properly terminate Power-down the reset or external
interrupt should not be executed before V
its normal operating level and must be held active long
enough for the oscillator to restart and stabilize (normally
less than 10 ms).
port data
port data
port data
port data
PORT 1
Power-down Mode
port data
address
port data
port data
PORT 2
port data
port data
port data
port data
PORT 3
Preliminary Specification
CC
CC
P8xC591
to the minimum
is restored to
PWM0/
PWM1
high
high
high
high

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