P87C591VFA/00,512 NXP Semiconductors, P87C591VFA/00,512 Datasheet - Page 23

• Manufacturer Part Number: P87C591VFA/00,512
• Description: IC 80C51 MCU 16K OTP 44-PLCC
• Manufacturer: NXP Semiconductors
• Series: 87Cr

Specifications of P87C591VFA/00,512

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: CAN, EBI/EMI, I²C, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Processor Series: P87C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: CAN, I2C, UART
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-1256-5; 935268182512; P87C591VFAA

Philips Semiconductors
11.3.1
The Power Off Flag (POF) is set by on-chip circuitry when
the V
bit can be set or cleared by software allowing a user to
determine if the reset is the result of a power-on or warm
after Power-down. The V
for the POF to remain unaffected by the V
11.3.2
11.3.5
Table 8
Table 9 Description of PCON bits
If logic 1s are written to PD and IDL at the same time, PD takes precedence. The reset value of PCON is (0XX00000).
2000 Jul 26
When the Idle mode is terminated by a hardware reset,
the device normally resumes program execution, from
where it left off, up to two machine cycles before the
internal reset algorithm takes control. On-chip hardware
inhibits access to internal RAM in this event, but access
to the port pins is not inhibited. To eliminate the
possibility of an unexpected write when Idle is
terminated by reset, the instruction following the one
that invokes Idle should not be one that writes to a port
pin or to external memory.
Single-chip 8-bit microcontroller with CAN controller
SMOD1
CC
BIT
7
7
6
5
4
3
2
1
0
level on the P8xC591 rises from 0 to 5 V. The POF
P
D
P
OWER
OWER
Power Control Register (address 87H)
ESIGN
O
C
C
SYMBOL
SMOD0
SMOD1
SMOD0
ONTROL
FF
ONSIDERATION
WLE
POF
GF1
GF0
IDL
PD
F
6
LAG
CC
R
level must remain above 3 V
EGISTER
Double Baud rate. When set to logic 1 the baud rate is doubled when the serial port
SIO0 is being used in Modes 1, 2 and 3.
Double Baud rate. Selects SM0/FE for SCON.7 bit.
Power Off flag.
Watchdog Load Enable. This flag must be set by software prior to loading T3
(Watchdog Timer). It is cleared when T3 is loaded.
General purpose flag bits.
Power-down mode select. Setting this bit activates Power-down mode. It can only be
set if the Watchdog timer enable bit ‘WDE’ is set to logic 0.
Idle mode select. Setting this bit activates the Idle mode.
POF
5
(PCON)
CC
level.
WLE
4
23
11.3.3
The ONCE
testing and debugging of systems without the device
having to be removed from the circuit. The ONCE Mode is
invoked by:
1. Pull ALE low while the device is in reset an PSEN is
2. Hold ALE low as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins go into
a float state, and the other port pins and ALE and PSEN
are weakly pulled high. The oscillator circuit remains
active. While the device is in this mode, an emulator or test
CPU can be used to drive the circuit. Normal operation is
restored when a normal reset is applied.
11.3.4
The ALE-Off bit, AO (AUXR.0) can be set to 0 disable the
ALE output. It will automatically become active when
required for external memory accesses and resume to the
OFF state after completing the external memory access.
GF1
high,
3
DESCRIPTION
ONCE
R
EDUCED
TM
(“On-Circuit Emulation”) Mode facilities
TM
GF0
M
EMI M
2
ODE
ODE
Preliminary Specification
PD
1
P8xC591
IDL
0