MC56F8037VLH Freescale Semiconductor, MC56F8037VLH Datasheet - Page 161

• Manufacturer Part Number: MC56F8037VLH
• Description: IC DSP 16BIT DUAL 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8037VLH

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 53
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MC56F8037EVM
• Interface Type: SCI, SPI, I2C
• Minimum Operating Temperature: - 40 C
• Package: 64LQFP
• Family Name: 56F8xxx
• Maximum Speed: 32 MHz
• On-chip Adc: 2(8-chx10-bit)
• On-chip Dac: 2-chx12-bit
• Number Of Timers: 5
• For Use With: MC56F8037EVM - BOARD EVAL FOR MC56F8037
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.14 JTAG Timing
Freescale Semiconductor
1. TCK frequency of operation must be less than 1/8 the processor rate.
TCK frequency of operation
TCK clock pulse width
TMS, TDI data set-up time
TMS, TDI data hold time
TCK low to TDO data valid
TCK low to TDO tri-state
(Output)
(Output
(Input)
(Input)
(Input)
TCK
TMS
TDO
TDO
TCK
TDI
V
Characteristic
M
)
= V
IL
+ (V
IH
Figure 10-17 Test Access Port Timing Diagram
Figure 10-16 Test Clock Input Timing Diagram
– V
1
IL
)/2
V
IH
t
t
TS
Symbol
56F8037/56F8027 Data Sheet, Rev. 7
DV
Table 10-19 JTAG Timing
t
f
t
t
t
t
PW
OP
DH
DS
DV
TS
t
PW
V
V
M
IL
Min
DC
50
—
—
5
5
1/f
SYS_CLK/8
OP
Input Data Valid
t
DS
Max
—
—
—
30
30
Output Data Valid
t
PW
V
M
MHz
Unit
ns
ns
ns
ns
ns
t
DH
See Figure
10-16
10-16
10-17
10-17
10-17
10-17
JTAG Timing
161