C8051F504-IM Silicon Laboratories Inc, C8051F504-IM Datasheet - Page 57

• Manufacturer Part Number: C8051F504-IM
• Description: IC 8051 MCU 32K FLASH 48-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F50xr

Specifications of C8051F504-IM

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-QFN
• Mfg Application Notes: LIN Bootloader AppNote
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), CAN, LIN, SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 40
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 32x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F500DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 32-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1527 - KIT DEV FOR C8051F50X
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1519-5

6.2. Output Code Formatting
The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code. When the
repeat count is set to 1, conversion codes are represented in 12-bit unsigned integer format and the output
conversion code is updated after each conversion. Inputs are measured from 0 to V
can be right-justified or left-justified, depending on the setting of the AD0LJST bit (ADC0CN.2). Unused
bits in the ADC0H and ADC0L registers are set to 0. Example codes are shown below for both right-justi-
fied and left-justified data.
When the ADC0 Repeat Count is greater than 1, the output conversion code represents the accumulated
result of the conversions performed and is updated after the last conversion in the series is finished. Sets
of 4, 8, or 16 consecutive samples can be accumulated and represented in unsigned integer format. The
repeat count can be selected using the AD0RPT bits in the ADC0CF register. The value must be right-jus-
tified (AD0LJST = 0), and unused bits in the ADC0H and ADC0L registers are set to 0. The following
example shows right-justified codes for repeat counts greater than 1. Notice that accumulating 2
is equivalent to left-shifting by n bit positions when all samples returned from the ADC have the same
value.
6.2.1. Settling Time Requirements
A minimum tracking time is required before an accurate conversion is performed. This tracking time is
determined by any series impedance, including the AMUX0 resistance, the ADC0 sampling capacitance,
and the accuracy required for the conversion.
Figure 6.5 shows the equivalent ADC0 input circuit. The required ADC0 settling time for a given settling
accuracy (SA) may be approximated by Equation 6.1. When measuring the Temperature Sensor output,
use the settling time specified in Table 5.10 on page 50. When measuring V
TAL
impedance and sampling capacitor values.
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
R
n is the ADC resolution in bits (10).
V
V
V
TOTAL
REF
REF
REF
VREF x 4095/4096
VREF x 2048/4096
VREF x 2047/4096
Input Voltage
reduces to R
Input Voltage
x 4095/4096
x 2048/4096
x 2047/4096
is the sum of the AMUX0 resistance and any external source resistance.
0
0
MUX
. See Table 5.9 for ADC0 minimum settling time requirements as well as the mux
Repeat Count = 4
Equation 6.1. ADC0 Settling Time Requirements
Right-Justified ADC0H:ADC0L
0x3FFC
0x1FFC
0x2000
0x0000
t
=
(AD0LJST = 0)
ln


0x0FFF
0x07FF
------- -
SA
0x0800
0x0000
2
n



R
Rev. 1.2
Repeat Count = 8
TOTAL
0x7FF8
0x3FF8
0x4000
0x0000
C
SAMPLE
Left-Justified ADC0H:ADC0L
C8051F50x/F51x
DD
(AD0LJST = 1)
with respect to GND, R
Repeat Count = 16
0xFFF0
0x8000
0x7FF0
0x0000
REF
0xFFF0
0x7FF0
0x8000
0x0000
x 4095/4096. Data
n
samples
TO-
57