PIC12LC671-04/P Microchip Technology, PIC12LC671-04/P Datasheet - Page 22

• Manufacturer Part Number: PIC12LC671-04/P
• Description: IC MCU OTP 1KX14 LV A/D 8DIP
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12LC671-04/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Processor Series: PIC12LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 8
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8
• Data Rom Size: 128 B
• Height: 3.3 mm
• Length: 9.27 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Width: 6.35 mm
• For Use With: 309-1051 - ADAPTER 8-DIP BD W/2 SO PLUGS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

PIC12C67X
4.3
The Program Counter (PC) is 13-bits wide. The low
byte comes from the PCL Register, which is a readable
and writable register. The high byte (PC<12:8>) is not
directly readable or writable and comes from PCLATH.
On any reset, the PC is cleared. Figure 4-3 shows the
two situations for the loading of the PC. The upper
example in the figure shows how the PC is loaded on a
write to PCL (PCLATH<4:0>
ple in the figure shows how the PC is loaded during a
CALL or GOTO instruction (PCLATH<4:3>
FIGURE 4-3:
4.3.1
A Computed GOTO is accomplished by adding an off-
set to the program counter (ADDWF PCL). When doing
a table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note “Implementing a Table Read" (AN556).
DS30561B-page 22
PC
PC
12
12 11 10
2
PCL and PCLATH
COMPUTED GOTO
PCH
5
PCLATH<4:3>
PCH
PCLATH
PCLATH<4:0>
8
PCLATH
8
LOADING OF PC IN
DIFFERENT SITUATIONS
7
7
PCL
PCL
PCH). The lower exam-
11
8
0
0
Instruction with
PCL as
Destination
ALU result
GOTO, CALL
Opcode <10:0>
PCH).
4.3.2
The PIC12C67X family has an 8-level deep x 13-bit
wide hardware stack. The stack space is not part of
either program or data space and the stack pointer is
not readable or writable. The PC is PUSHed onto the
stack when a CALL instruction is executed or an inter-
rupt causes a branch. The stack is POPed in the event
of a RETURN, RETLW or a RETFIE instruction execu-
tion. PCLATH is not affected by a PUSH or POP oper-
ation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
4.4
The
PCLATH<4:3>, which are used to access program
memory when more than one page is available. The
use of PCLATH<4:3> as general purpose read/write
bits for the PIC12C67X is not recommended since this
may affect upward compatibility with future products.
Note 1: There are no status bits to indicate stack
PIC12C67X
2: There are no instructions/mnemonics
STACK
Program Memory Paging
overflow or stack underflow conditions.
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW, and RETFIE
instructions, or the vectoring to an inter-
rupt address.
ignores
1999 Microchip Technology Inc.
both
paging
bits