PIC18F45J10-I/ML Microchip Technology, PIC18F45J10-I/ML Datasheet - Page 154

• Manufacturer Part Number: PIC18F45J10-I/ML
• Description: IC PIC MCU FLASH 16KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F45J10-I/ML

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Controller Family/series: PIC18
• No. Of I/o's: 21
• Ram Memory Size: 1024Byte
• Cpu Speed: 40MHz
• No. Of Timers: 3
• Interface: I2C, SPI, USART
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: MSSP, SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM163022, DM183040
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164336 - MODULE SOCKET FOR PM3 28/44QFNAC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180013 - MODULE PLUG-IN 18F45J10 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28PXLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

(SSPxSTAT<0>), and the interrupt flag bit, SSPxIF, are
PIC18F45J10 FAMILY
16.3.2
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCKx is the clock output)
• Slave mode (SCKx is the clock input)
• Clock Polarity (Idle state of SCKx)
• Data Input Sample Phase (middle or end of data
• Clock Edge (output data on rising/falling edge of
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
Each MSSP consists of a transmit/receive shift register
(SSPxSR) and a buffer register (SSPxBUF). The
SSPxSR shifts the data in and out of the device, MSb
first. The SSPxBUF holds the data that was written to the
SSPxSR until the received data is ready. Once the 8 bits
of data have been received, that byte is moved to the
SSPxBUF register. Then, the Buffer Full detect bit, BF
set. This double-buffering of the received data
(SSPxBUF) allows the next byte to start reception before
reading the data that was just received. Any write to the
EXAMPLE 16-1:
DS39682E-page 152
LOOP
output time)
SCKx)
BTFSS
BRA
MOVF
MOVWF
MOVF
MOVWF
OPERATION
SSP1STAT, BF
LOOP
SSP1BUF, W
RXDATA
TXDATA, W
SSP1BUF
LOADING THE SSP1BUF (SSP1SR) REGISTER
;Has data been received (transmit complete)?
;No
;WREG reg = contents of SSP1BUF
;Save in user RAM, if data is meaningful
;W reg = contents of TXDATA
;New data to xmit
successfully.
written. If the interrupt method is not going to be used,
loading
SSPxBUF register during transmission/reception of data
will be ignored and the Write Collision detect bit, WCOL
(SSPxCON1<7>), will be set. User software must clear
the WCOL bit so that it can be determined if the following
write(s)
When the application software is expecting to receive
valid data, the SSPxBUF should be read before the next
byte of data to transfer is written to the SSPxBUF. The
Buffer Full bit, BF (SSPxSTAT<0>), indicates when
SSPxBUF has been loaded with the received data
(transmission is complete). When the SSPxBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP interrupt
is used to determine when the transmission/reception
has completed. The SSPxBUF must be read and/or
then software polling can be done to ensure that a write
collision does not occur. Example 16-1 shows the
transmission.
The SSPxSR is not directly readable or writable and
can only be accessed by addressing the SSPxBUF
register. Additionally, the SSPxSTAT register indicates
the various status conditions.
of
to
the
the
SSP1BUF
SSPxBUF
© 2009 Microchip Technology Inc.
(SSP1SR)
register
completed
for
data