PIC18F45J10-I/ML Microchip Technology, PIC18F45J10-I/ML Datasheet - Page 357

• Manufacturer Part Number: PIC18F45J10-I/ML
• Description: IC PIC MCU FLASH 16KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F45J10-I/ML

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Controller Family/series: PIC18
• No. Of I/o's: 21
• Ram Memory Size: 1024Byte
• Cpu Speed: 40MHz
• No. Of Timers: 3
• Interface: I2C, SPI, USART
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: MSSP, SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM163022, DM183040
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164336 - MODULE SOCKET FOR PM3 28/44QFNAC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180013 - MODULE PLUG-IN 18F45J10 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28PXLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

E
Effect on Standard PIC Instructions ................................. 296
Effects of Power-Managed Modes on
Electrical Characteristics .................................................. 303
Enhanced Capture/Compare/PWM (ECCP) .................... 135
Enhanced PWM Mode. See PWM (ECCP Module). ........ 137
Enhanced Universal Synchronous Asynchronous
Equations
Errata ................................................................................... 6
EUSART
Extended Instruction Set
External Clock Input (EC Modes) ....................................... 28
© 2009 Microchip Technology Inc.
Various Clock Sources ............................................... 32
Associated Registers ............................................... 148
Capture and Compare Modes .................................. 136
Capture Mode. See Capture (ECCP Module).
Outputs and Configuration ....................................... 136
Pin Configurations for ECCP1 Modes ...................... 136
PWM Mode. See PWM (ECCP Module).
Standard PWM Mode ............................................... 136
Timer Resources ...................................................... 136
Receiver Transmitter (EUSART). See EUSART.
A/D Acquisition Time ................................................ 220
A/D Minimum Charging Time ................................... 220
Asynchronous Mode ................................................ 203
Baud Rate Generator
Baud Rate Generator (BRG) .................................... 197
Synchronous Master Mode ...................................... 209
Synchronous Slave Mode ........................................ 212
ADDFSR .................................................................. 292
ADDULNK ................................................................ 292
and Using MPLAB IDE Tools ................................... 298
CALLW ..................................................................... 293
Considerations for Use ............................................ 296
MOVSF .................................................................... 293
MOVSS .................................................................... 294
PUSHL ..................................................................... 294
SUBFSR .................................................................. 295
SUBULNK ................................................................ 295
Syntax ...................................................................... 291
12-Bit Break Transmit and Receive ................. 208
Associated Registers, Receive ........................ 206
Associated Registers, Transmit ....................... 204
Auto-Wake-up on Sync Break ......................... 206
Receiver ........................................................... 205
Setting Up 9-Bit Mode with
Transmitter ....................................................... 203
Operation in Power-Managed Mode ................ 197
Associated Registers ....................................... 198
Auto-Baud Rate Detect .................................... 201
Baud Rate Error, Calculating ........................... 198
Baud Rates, Asynchronous Modes ................. 199
High Baud Rate Select (BRGH Bit) ................. 197
Sampling .......................................................... 197
Associated Registers, Receive ........................ 211
Associated Registers, Transmit ....................... 210
Reception ......................................................... 211
Transmission ................................................... 209
Associated Registers, Receive ........................ 213
Associated Registers, Transmit ....................... 212
Reception ......................................................... 213
Transmission ................................................... 212
Address Detect ........................................ 205
PIC18F45J10 FAMILY
F
Fail-Safe Clock Monitor ........................................... 235, 245
Fast Register Stack ........................................................... 55
Firmware Instructions ...................................................... 249
Flash Configuration Words .............................................. 235
Flash Program Memory ..................................................... 71
FSCM. See Fail-Safe Clock Monitor.
G
GOTO .............................................................................. 270
H
Hardware Multiplier ............................................................ 81
I
I/O Ports ............................................................................ 97
I
2
C Mode (MSSP)
Interrupts in Power-Managed Modes ...................... 246
POR or Wake-up from Sleep ................................... 246
WDT During Oscillator Failure ................................. 245
Associated Registers ................................................. 79
Control Registers ....................................................... 72
Erase Sequence ........................................................ 76
Erasing ...................................................................... 76
Operation During Code-Protect ................................. 79
Reading ..................................................................... 75
Table Pointer
Table Pointer Boundaries .......................................... 74
Table Reads and Table Writes .................................. 71
Write Sequence ......................................................... 77
Writing To .................................................................. 77
Introduction ................................................................ 81
Operation ................................................................... 81
Performance Comparison .......................................... 81
Acknowledge Sequence Timing .............................. 185
Associated Registers ............................................... 192
Baud Rate Generator .............................................. 178
Bus Collision
Clock Arbitration ...................................................... 179
Clock Stretching ...................................................... 171
Clock Synchronization and the CKP Bit .................. 172
Effects of a Reset .................................................... 186
General Call Address Support ................................. 175
I
Master Mode ............................................................ 176
2
C Clock Rate w/BRG ............................................ 178
EECON1 and EECON2 ..................................... 72
TABLAT (Table Latch) ....................................... 74
TBLPTR (Table Pointer) .................................... 74
Boundaries Based on Operation ....................... 74
Protection Against Spurious Writes ................... 79
Unexpected Termination ................................... 79
Write Verify ........................................................ 79
During a Repeated Start Condition .................. 190
During a Stop Condition .................................. 191
10-Bit Slave Receive Mode (SEN = 1) ............ 171
10-Bit Slave Transmit Mode ............................ 171
7-Bit Slave Receive Mode (SEN = 1) .............. 171
7-Bit Slave Transmit Mode .............................. 171
Baud Rate Generator ...................................... 178
Operation ......................................................... 177
Reception ........................................................ 182
Repeated Start Condition Timing .................... 181
Start Condition Timing ..................................... 180
Transmission ................................................... 182
DS39682E-page 355