PIC18F45J10-I/ML Microchip Technology, PIC18F45J10-I/ML Datasheet - Page 362

• Manufacturer Part Number: PIC18F45J10-I/ML
• Description: IC PIC MCU FLASH 16KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F45J10-I/ML

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Controller Family/series: PIC18
• No. Of I/o's: 21
• Ram Memory Size: 1024Byte
• Cpu Speed: 40MHz
• No. Of Timers: 3
• Interface: I2C, SPI, USART
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: MSSP, SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM163022, DM183040
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164336 - MODULE SOCKET FOR PM3 28/44QFNAC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180013 - MODULE PLUG-IN 18F45J10 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28PXLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F45J10 FAMILY
Timer0 .............................................................................. 115
Timer1 .............................................................................. 119
Timer2 .............................................................................. 125
Timing Diagrams
DS39682E-page 360
Associated Registers ............................................... 117
Clock Source Select (T0CS Bit) ............................... 116
Operation ................................................................. 116
Overflow Interrupt .................................................... 117
Prescaler .................................................................. 117
Prescaler Assignment (PSA Bit) .............................. 117
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 117
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 116
Source Edge Select (T0SE Bit) ................................ 116
Switching Prescaler Assignment .............................. 117
16-Bit Read/Write Mode ........................................... 121
Associated Registers ............................................... 124
Interrupt .................................................................... 122
Operation ................................................................. 120
Oscillator .......................................................... 119, 121
Oscillator, as Secondary Clock .................................. 30
Overflow Interrupt .................................................... 119
Resetting, Using the ECCP/CCP
Special Event Trigger (ECCP) ................................. 136
TMR1H Register ...................................................... 119
TMR1L Register ....................................................... 119
Use as a Clock Source ............................................ 122
Use as a Real-Time Clock ....................................... 123
Associated Registers ............................................... 126
Interrupt .................................................................... 126
Operation ................................................................. 125
Output ...................................................................... 126
PR2 Register .................................................... 132, 137
TMR2-to-PR2 Match Interrupt .......................... 132, 137
A/D Conversion ........................................................ 334
Acknowledge Sequence .......................................... 185
Asynchronous Reception ......................................... 206
Asynchronous Transmission .................................... 204
Asynchronous Transmission (Back to Back) ........... 204
Automatic Baud Rate Calculation ............................ 202
Auto-Wake-up Bit (WUE) During
Auto-Wake-up Bit (WUE) During Sleep ................... 207
Baud Rate Generator with Clock Arbitration ............ 179
BRG Overflow Sequence ......................................... 202
BRG Reset Due to SDAx Arbitration During
Brown-out Reset (BOR) ........................................... 322
Bus Collision During a Repeated
Bus Collision During a Repeated
Bus Collision During a
Bus Collision During a
Bus Collision During a
Bus Collision During
Bus Collision for Transmit and Acknowledge ........... 187
Capture/Compare/PWM
Layout Considerations ..................................... 122
Special Event Trigger ....................................... 123
Normal Operation ............................................. 207
Start Condition ................................................. 189
Start Condition (Case 1) .................................. 190
Start Condition (Case 2) .................................. 190
Start Condition (SCLx = 0) ............................... 189
Stop Condition (Case 1) ................................... 191
Stop Condition (Case 2) ................................... 191
Start Condition (SDAx Only) ............................ 188
(Including ECCP Module) ................................ 324
CLKO and I/O .......................................................... 321
Clock Synchronization ............................................. 172
Clock/Instruction Cycle .............................................. 56
EUSART Synchronous Receive (Master/Slave) ...... 333
EUSART Synchronous Transmission
Example SPI Master Mode (CKE = 0) ..................... 325
Example SPI Master Mode (CKE = 1) ..................... 326
Example SPI Slave Mode (CKE = 0) ....................... 327
Example SPI Slave Mode (CKE = 1) ....................... 328
External Clock (All Modes Except PLL) ................... 319
Fail-Safe Clock Monitor ........................................... 246
First Start Bit Timing ................................................ 180
Full-Bridge PWM Output .......................................... 141
Half-Bridge PWM Output ......................................... 140
I
I
I
I
I
I
I
I
I
I
I
I
Master SSP I
Master SSP I
Parallel Slave Port (PSP) Read ............................... 114
Parallel Slave Port (PSP) Write ............................... 114
PWM Auto-Shutdown (PRSEN = 0,
PWM Auto-Shutdown (PRSEN = 1,
PWM Direction Change ........................................... 143
PWM Direction Change at Near
PWM Output ............................................................ 132
Repeated Start Condition ........................................ 181
Reset, Watchdog Timer (WDT), Oscillator Start-up
Send Break Character Sequence ............................ 208
Slave Synchronization ............................................. 155
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ......................................... 154
SPI Mode (Slave Mode, CKE = 0) ........................... 156
SPI Mode (Slave Mode, CKE = 1) ........................... 156
Synchronous Reception
Synchronous Transmission ..................................... 209
Synchronous Transmission (Through TXEN) .......... 210
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock .......................... 323
Transition for Entry to Idle Mode ................................ 39
Transition for Entry to SEC_RUN Mode .................... 36
Transition for Entry to Sleep Mode ............................ 38
Transition for Two-Speed Start-up (INTRC) ............ 244
2
2
2
2
2
2
2
2
2
2
2
2
C Bus Data ............................................................ 329
C Bus Start/Stop Bits ............................................ 329
C Master Mode (7 or 10-Bit Transmission) ........... 183
C Master Mode (7-Bit Reception) .......................... 184
C Slave Mode (10-Bit Reception, SEN = 0) .......... 169
C Slave Mode (10-Bit Reception, SEN = 1) .......... 174
C Slave Mode (10-Bit Transmission) .................... 170
C Slave Mode (7-Bit Reception, SEN = 0) ............ 167
C Slave Mode (7-Bit Reception, SEN = 1) ............ 173
C Slave Mode (7-Bit Transmission) ...................... 168
C Slave Mode General Call Address
C Stop Condition Receive or Transmit Mode ........ 186
(Master/Slave) ................................................. 333
Sequence (7 or 10-Bit Address Mode) ............ 175
Auto-Restart Disabled) .................................... 146
Auto-Restart Enabled) ..................................... 146
100% Duty Cycle ............................................. 143
Timer (OST) and Power-up Timer (PWRT) ..... 322
V
(Master Mode, SREN) ..................................... 211
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
DD
Rise > T
2
2
C Bus Data ........................................ 331
C Bus Start/Stop Bits ........................ 331
PWRT
© 2009 Microchip Technology Inc.
DD
) ............................................ 45
, V
DD
DD
DD
), Case 1 ...................... 45
), Case 2 ...................... 45
Rise /Tpwrt) ............... 44
DD
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