PIC18LF4420-I/PT Microchip Technology, PIC18LF4420-I/PT Datasheet - Page 133

• Manufacturer Part Number: PIC18LF4420-I/PT
• Description: IC MCU FLASH 8KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF4420-I/PT

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 36
• Interface Type: I2C/SPI/USART
• On-chip Adc: 13-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.7
Following a Timer1 interrupt and an update to the
TMR1 registers, the Timer1 module uses a falling edge
on its clock source to trigger the next register update on
the rising edge. If the update is completed after the
clock input has fallen, the next rising edge will not be
counted.
If the application can reliably update TMR1 before the
timer input goes low, no additional action is needed.
Otherwise, an adjusted update can be performed
following a later Timer1 increment. This can be done by
EXAMPLE 12-1:
© 2008 Microchip Technology Inc.
RTCinit
RTCisr
Considerations in Asynchronous
Counter Mode
MOVLW
MOVWF
CLRF
MOVLW
MOVWF
CLRF
CLRF
MOVLW
MOVWF
BSF
RETURN
BTFSC
BRA
BTFSS
BRA
BSF
BCF
INCF
MOVLW
CPFSGT secs
RETURN
CLRF
INCF
MOVLW
CPFSGT mins
RETURN
CLRF
INCF
MOVLW
CPFSGT hours
RETURN
CLRF
RETURN
IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
80h
TMR1H
TMR1L
b’00001111’
T1CON
secs
mins
.12
hours
PIE1, TMR1IE
TMR1L,0
$-2
TMR1L,0
$-2
TMR1H, 7
PIR1, TMR1IF
secs, F
.59
secs
mins, F
.59
mins
hours, F
.23
hours
; Preload TMR1 register pair
; for 1 second overflow
; Configure for external clock,
; Asynchronous operation, external oscillator
; Initialize timekeeping registers
;
; Enable Timer1 interrupt
; Start ISR here
; Insert the next 4 lines of code when TMR1
; can not be reliably updated before clock pulse goes low
; wait for TMR1L<0> to become clear
; (may already be clear)
; wait for TMR1L<0> to become set
; TMR1 has just incremented
; If TMR1 update can be completed before clock pulse goes low
; Preload for 1 sec overflow
; Clear interrupt flag
; Increment seconds
; 60 seconds elapsed?
; No, done
; Clear seconds
; Increment minutes
; 60 minutes elapsed?
; No, done
; clear minutes
; Increment hours
; 24 hours elapsed?
; No, done
; Reset hours
; Done
PIC18F2420/2520/4420/4520
monitoring TMR1L within the interrupt routine until it
increments, and then updating the TMR1H:TMR1L
register pair while the clock is low, or one-half of the
period of the clock source. Assuming that Timer1 is
being used as a Real-Time Clock, the clock source is a
32.768 kHz crystal oscillator; in this case, one half
period of the clock is 15.25 μs.
The Real-Time Clock application code in Example 12-1
shows a typical ISR for Timer1, as well as the optional
code required if the update cannot be done reliably
within the required interval.
DS39631E-page 131