PIC18LF4420-I/PT Microchip Technology, PIC18LF4420-I/PT Datasheet - Page 83

• Manufacturer Part Number: PIC18LF4420-I/PT
• Description: IC MCU FLASH 8KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF4420-I/PT

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 36
• Interface Type: I2C/SPI/USART
• On-chip Adc: 13-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

EXAMPLE 6-3:
6.5.2
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
6.5.3
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. If the write operation is interrupted
by a MCLR Reset or a WDT Time-out Reset during
normal operation, the user can check the WRERR bit
and rewrite the location(s) as needed.
TABLE 6-2:
© 2008 Microchip Technology Inc.
TBLPTRU
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
TABLAT
INTCON
EECON2
EECON1
IPR2
PIR2
PIE2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
PROGRAM_MEMORY
Name
Required
Sequence
WRITE VERIFY
UNEXPECTED TERMINATION OF
WRITE OPERATION
Program Memory Table Latch
EEPROM Control Register 2 (not a physical register)
GIE/GIEH PEIE/GIEL TMR0IE
OSCFIP
OSCFIE
OSCFIF
EEPGD
Bit 7
—
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
BSF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
CFGS
CMIP
CMIE
CMIF
Bit 6
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
EECON1, WREN
—
bit 21
Bit 5
—
—
—
—
PIC18F2420/2520/4420/4520
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
INT0IE
FREE
EEIP
EEIF
EEIE
Bit 4
; point to Flash program memory
; access Flash program memory
; enable write to memory
; disable interrupts
; write 55h
; write 0AAh
; start program (CPU stall)
; re-enable interrupts
; disable write to memory
WRERR
BCLIP
BCLIE
BCLIF
RBIE
Bit 3
6.5.4
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 23.0 “Special Features of
the CPU” for more detail.
6.6
See Section 23.5 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
TMR0IF
HLVDIP
HLVDIF
HLVDIE
Flash Program Operation During
Code Protection
WREN
Bit 2
PROTECTION AGAINST
SPURIOUS WRITES
TMR3IP
TMR3IF
TMR3IE
INT0IF
Bit 1
WR
CCP2IP
CCP2IF
CCP2IE
RBIF
Bit 0
RD
DS39631E-page 81
Values on
Reset
page
49
49
49
49
49
51
51
52
52
52