PIC18LF4420-I/PT Microchip Technology, PIC18LF4420-I/PT Datasheet - Page 317

• Manufacturer Part Number: PIC18LF4420-I/PT
• Description: IC MCU FLASH 8KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF4420-I/PT

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 36
• Interface Type: I2C/SPI/USART
• On-chip Adc: 13-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADDWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2008 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
OFST
FSR2
Contents
of 0A2Ch
W
Contents
of 0A2Ch
Q1
ADD W to Indexed
(Indexed Literal Offset mode)
ADDWF
0 ≤ k ≤ 95
d ∈ [0,1]
(W) + ((FSR2) + k) → dest
N, OV, C, DC, Z
The contents of W are added to the
contents of the register indicated by
FSR2, offset by the value ‘k’.
If ‘d’ is ‘0’, the result is stored in W. If ‘d’
is ‘1’, the result is stored back in
register ‘f’ (default).
1
1
ADDWF
Read ‘k’
0010
Q2
=
=
=
=
=
=
[OFST] , 0
[k] {,d}
01d0
17h
2Ch
0A00h
20h
37h
20h
Process
Data
Q3
kkkk
destination
Write to
PIC18F2420/2520/4420/4520
Q4
kkkk
BSF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
SETF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Q Cycle Activity:
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
Decode
FLAG_OFST
FSR2
Contents
of 0A0Ah
Contents
of 0A0Ah
OFST
FSR2
Contents
of 0A2Ch
Contents
of 0A2Ch
Q1
Q1
register ‘f’
BSF
Bit Set Indexed
(Indexed Literal Offset mode)
BSF [k], b
0 ≤ f ≤ 95
0 ≤ b ≤ 7
1 → ((FSR2) + k)<b>
None
Bit ‘b’ of the register indicated by FSR2,
offset by the value ‘k’, is set.
1
1
Set Indexed
(Indexed Literal Offset mode)
SETF [k]
0 ≤ k ≤ 95
FFh → ((FSR2) + k)
None
The contents of the register indicated by
FSR2, offset by ‘k’, are set to FFh.
1
1
SETF
Read ‘k’
Read
1000
0110
Q2
Q2
=
=
=
=
=
=
=
=
2Ch
0A00h
00h
FFh
[FLAG_OFST], 7
[OFST]
bbb0
1000
0Ah
0A00h
55h
D5h
Process
Process
Data
Data
Q3
Q3
DS39631E-page 315
kkkk
kkkk
destination
Write to
register
Write
Q4
Q4
kkkk
kkkk