ST72F361J9T6 STMicroelectronics, ST72F361J9T6 Datasheet - Page 221

• Manufacturer Part Number: ST72F361J9T6
• Description: IC MCU 8BIT 60K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F361J9T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: LINSCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST72F36X-SK/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

IMPORTANT NOTES (Cont’d)
Figure 131.LINSCI Interrupt Routine
16.1.6 TIMD set simultaneously with OC
interrupt
If the 16-bit timer is disabled at the same time the
output compare event occurs then the output com-
pare flag gets locked and cannot be cleared be-
fore the timer is enabled again.
Impact on the application: If output compare in-
terrupt is enabled, then the output compare flag
cannot be cleared in the timer interrupt routine.
Consequently the interrupt service routine is called
repeatedly and the application get stuck which
causes the watchdog reset if enabled by the appli-
cation.
Workaround: Disable the timer interrupt before
disabling the timer. Again while enabling, first ena-
ble the timer, then the timer interrupts.
Perform the following to disable the timer:
– TACR1 or TBCR1 = 0x00h; // Disable the com-
– TACSR | or TBCSR | = 0x40; // Disable the timer
– Perform the following to enable the timer again:
– TACSR & or TBCSR &= ~0x40; // Enable the tim-
– TACR1 or TBCR1 = 0x40; // Enable the compare
pare interrupt
er
interrupt
@interrupt void LINSCI_IT ( void ) /* LINSCI interrupt routine */
{
}
/* clear flags */
SCISR_buffer = SCISR;
SCIDR_buffer = SCIDR;
if ( SCISR_buffer & LHE )/* header error ? */
{
}
if (!LHLR)/* header time-out? */
{
}
{
}
if ( !(SCICR2 & RWU) )/* active mode ? */
SCISR;
SCIDR;/* Clear RDRF flag */
SCICR2 |= RWU;/* set mute mode */
SCISR;
SCIDR;/* Clear RDRF flag */
SCICR2 |= RWU;/* set mute mode */
_asm("rim");/* enable interrupts */
_asm("sim");/* disable interrupts */
16.2 FLASH/FASTROM DEVICES ONLY
16.2.1 LINSCI Wrong Break Duration
SCI mode
A single break character is sent by setting and re-
setting the SBK bit in the SCICR2 register. In
some cases, the break character may have a long-
er duration than expected:
- 20 bits instead of 10 bits if M = 0
- 22 bits instead of 11 bits if M = 1
In the same way, as long as the SBK bit is set,
break characters are sent to the TDO pin. This
may lead to generate one break more than expect-
ed.
Occurrence
The occurrence of the problem is random and pro-
portional to the baud rate. With a transmit frequen-
cy
SCIBRR = 0xC9), the wrong break duration occur-
rence is around 1%.
Workaround
If this wrong duration is not compliant with the
communication protocol in the application, soft-
ware can request that an Idle line be generated
before the break character. In this case, the break
of
19200
Example using Cosmic compiler syntax
baud
(f
CPU
= 8 MHz
ST72361
221/225
and