ST72F361J9T6 STMicroelectronics, ST72F361J9T6 Datasheet - Page 28

• Manufacturer Part Number: ST72F361J9T6
• Description: IC MCU 8BIT 60K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F361J9T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: LINSCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST72F36X-SK/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST72361
7 INTERRUPTS
7.1 INTRODUCTION
The ST7 enhanced interrupt management pro-
vides the following features:
■
■
■
This interrupt management is based on:
– Bit 5 and bit 3 of the CPU CC register (I1:0),
– Interrupt software priority registers (ISPRx),
– Fixed interrupt vector addresses located at the
This enhanced interrupt controller guarantees full
upward compatibility with the standard (not nest-
ed) ST7 interrupt controller.
7.2 MASKING AND PROCESSING FLOW
The interrupt masking is managed by the I1 and I0
bits of the CC register and the ISPRx registers
which give the interrupt software priority level of
Figure 17. Interrupt Processing Flowchart
28/225
high addresses of the memory map (FFE0h to
FFFFh) sorted by hardware priority order.
– Up to 4 software programmable nesting levels
– Up to 16 interrupt vectors fixed by hardware
– 2 non maskable events: RESET, TRAP
– 1 maskable Top Level Event: TLI
Hardware interrupts
Software interrupt (TRAP)
Nested or concurrent interrupt management
with
management:
flexible
RESTORE PC, X, A, CC
FROM STACK
RESET
interrupt
priority
Y
and
INSTRUCTION
INTERRUPT
INSTRUCTION
FETCH NEXT
PENDING
EXECUTE
N
“IRET”
N
level
Y
each interrupt vector (see
ing flow is shown in
When an interrupt request has to be serviced:
– Normal processing is suspended at the end of
– The PC, X, A and CC registers are saved onto
– I1 and I0 bits of CC register are set according to
– The PC is then loaded with the interrupt vector of
The interrupt service routine should end with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction,
the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.
Table 7. Interrupt Software Priority Levels
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable)
Interrupt software priority
the current instruction execution.
the stack.
the corresponding values in the ISPRx registers
of the serviced interrupt vector.
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
“Interrupt Mapping” table for vector addresses).
STAYS PENDING
THE INTERRUPT
Interrupt has the same or a
LOAD I1:0 FROM INTERRUPT SW REG.
LOAD PC FROM INTERRUPT VECTOR
lower software priority
than current one
STACK PC, X, A, CC
Figure
Table
17.
Level
High
Low
6). The process-
I1:0
TLI
N
I1
1
0
1
Y
I0
0
1
0
1