MC9S08GT8ACFBE Freescale Semiconductor, MC9S08GT8ACFBE Datasheet - Page 84

• Manufacturer Part Number: MC9S08GT8ACFBE
• Description: IC MCU 8K FLASH 1K RAM 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08GT8ACFBE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Processor Series: S08GT
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: M68EVB908GB60E, M68DEMO908GB60E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• For Use With: M68DEMO908GB60E - BOARD DEMO MC9S08GB60M68EVB908GB60E - BOARD EVAL FOR MC9S08GB60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Parallel Input/Output
6.2.5
Port E is an 6-bit port shared with the SCI1 module, SPI1 module, and general-purpose I/O. When the SCI
or SPI modules are enabled, the pin direction will be controlled by the module function.
Port E pins are available as general-purpose I/O pins controlled by the port E data (PTED), data direction
(PTEDD), pullup enable (PTEPE), and slew rate control (PTESE) registers. Refer to
I/O
When the SCI1 module is enabled, PTE0 serves as the SCI1 module’s transmit pin (TxD1) and PTE1
serves as the receive pin (RxD1). Refer to
more information about using PTE0 and PTE1 as SCI pins.
When the SPI module is enabled, PTE2 serves as the SPI module’s slave select pin (SS1), PTE3 serves as
the master-in slave-out pin (MISO1), PTE4 serves as the master-out slave-in pin (MOSI1), and PTE5
serves as the SPI clock pin (SPSCK1). Refer to
more information about using PTE5–PTE2 as SPI pins.
6.2.6
Port G is an 4-bit port which is shared among the background/mode select function, oscillator, and
general-purpose I/O. When the background/mode select function or oscillator is enabled, the pin direction
will be controlled by the module function.
Port G pins are available as general-purpose I/O pins controlled by the port G data (PTGD), data direction
(PTGDD), pullup enable (PTGPE), and slew rate control (PTGSE) registers. Refer to
I/O
The internal pullup for PTG0 is enabled when the background/mode select function is enabled, regardless
of the state of PTGPE0. During reset, the BKGD/MS pin functions as a mode select pin. After the MCU
exits
be configured to be a general-purpose output pin. Refer to
(SOPT),” for selecting BKGD or PTG0. Refer to
Interrupts, and System
about using this pin.
The ICG module can be configured to use PTG2–PTG1 ports as crystal oscillator or external clock pins.
84
Port G
Port E
Controls”
Controls,”
reset, the BKGD/MS pin becomes the background communications input/output pin. The PTG0 can
Port E, SCI1, and SPI
Port G, BKGD/MS, and Oscillator
for more information about general-purpose I/O control.
for more information about general-purpose I/O control.
MCU Pin:
MCU Pin:
Configuration,”
Bit 7
Bit 7
0
0
MC9S08GT16A/GT8A Data Sheet, Rev. 1
0
Figure 6-7. Port G Pin Names
Figure 6-6. Port E Pin Names
6
0
6
and
Chapter 11, “Serial Communications Interface
Chapter 15, “Development
SPSCK
PTE5/
5
0
Chapter 12, “Serial Peripheral Interface (S08SPIV3)
5
Chapter 3, “Modes of
PTE4/
MOSI
4
0
4
Section 5.7.4, “System Options Register
PTG3
PTE3/
MISO
3
3
Support,” for more information
Operation,”,
EXTAL
PTG2/
PTE2/
SS
2
2
PTG1/
PTE1/
XTAL
RxD1
Section 6.3, “Parallel
Section 6.3, “Parallel
Freescale Semiconductor
Chapter 5, “Resets,
1
1
(S08SCIV1)”
BKGD/MS
PTE0/
PTG0/
TxD1
Bit 0
Bit 0
for
for