MC9S12XA256CAL Freescale Semiconductor, MC9S12XA256CAL Datasheet - Page 1009

IC MCU 256K FLASH 112-LQFP

MC9S12XA256CAL

Manufacturer Part Number
MC9S12XA256CAL
Description
IC MCU 256K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheets

Specifications of MC9S12XA256CAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
91
Eeprom Memory Size
4KB
Ram Memory Size
16KB
Cpu Speed
80MHz
No. Of Timers
1
No. Of Pwm Channels
8
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Processor Series
S12XA
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
91
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 16 Channel)
Package
112LQFP
Family Name
HCS12
Maximum Speed
40 MHz
Operating Supply Voltage
2.5|5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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WOMM[7:0]
Reset
This register configures the output pins as wired-OR. If enabled the output is driven active low only
(open-drain). A logic level of “1” is not driven. It applies also to the CAN outputs and allows a
multipoint connection of several serial modules. This bit has no influence on pins used as inputs.
Field
24.0.5.33 Module Routing Register (MODRR)
1. Register implemented, function disabled: Written values can be read back.
Read: Anytime.
Write: Anytime.
This register configures the re-routing of CAN0, CAN4, SPI0, SPI1 on alternative ports.
7–0
W
R
Module
Wired-OR Mode Port M
0 Output buffers operate as push-pull outputs.
1 Output buffers operate as open-drain outputs.
CAN0
CAN4
SPI0
SPI1
7
0
0
= Unimplemented or Reserved
6
x
x
x
x
x
x
x
x
x
x
x
x
MODRR6
5
0
1
0
x
x
x
x
x
x
x
x
x
x
6
Figure 24-35. Module Routing Register (MODRR)
1
4
0
1
x
x
x
x
x
x
x
x
x
x
MODRR
Table 24-34. Module Routing Summary
Table 24-33. WOMM Field Descriptions
MODRR5
3
x
x
x
x
0
0
1
1
x
x
x
x
5
0
2
x
x
x
x
0
1
0
1
x
x
x
x
1
0
0
1
1
x
x
x
x
x
x
x
x
MODRR4
0
0
1
0
1
x
x
x
x
x
x
x
x
0
4
Description
MISO
PM2
PS4
PP0
PH0
RXCAN
MODRR3
PM0
PM2
PM4
PM4
PM6
PJ6
PJ6
3
0
MOSI
PM4
PH1
PS5
PP1
Related Pins
Reserved
MODRR2
0
2
SCK
PM5
PS6
PP2
PH2
TXCAN
PM1
PM3
PM5
PM5
PM7
PJ7
PJ7
MODRR1
1
0
PM3
PH3
PS7
PP3
SS
MODRR0
0
0

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